[PATCH] Implement floating point compare for mips fast-isel

[reed kotler]

On 10/03/2014 03:33 AM, Daniel Sanders wrote:
> I'm holding back on the conditional LGTM for now since I would like to see how you solve the 64-bit FPU cases both here and in D5562 first.
>
> ================
> Comment at: lib/Target/Mips/MipsFastISel.cpp:625
> @@ +624,3 @@
> +    case CmpInst::FCMP_OEQ:
> +      Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
> +      CondMovOpc = Mips::MOVT_I;
> ----------------
> C_EQ_D32 needs to be C_EQ_D64 for 64-bit FPU's and we don't guard against this.
>
> Similarly for the other compares.
>
> ================
> Comment at: lib/Target/Mips/MipsFastISel.cpp:640-647
> @@ +639,10 @@
> +      break;
> +    case CmpInst::FCMP_OGT:
> +      Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
> +      CondMovOpc = Mips::MOVF_I;
> +      break;
> +    case CmpInst::FCMP_OGE:
> +      Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
> +      CondMovOpc = Mips::MOVF_I;
> +      break;
> +    default:
> ----------------
> These two aren't correct when one of the operands is NaN. 'NaN ogt 0.0' is false because they are unordered, but '!(NaN ole 0.0)' is true. Swap the LHS/RHS instead.
A typo on my part. Will fix there two.
> ================
> Comment at: test/CodeGen/Mips/Fast-ISel/fpcmpa.ll:20
> @@ +19,3 @@
> +; CHECK:  c.eq.s  $f{{[0-9]+}}, $f{{[0-9]+}}
> +; CHECK:  movt  ${{[0-9]+}}, ${{[0-9]+}}, $fcc0
> +
> ----------------
> We ought to check that the registers are in the right order.
>
> Likewise for the tests below.
>
> http://reviews.llvm.org/D5567
>
>