[PATCH] [AArch64] Generate vector signed/unsigned mul and mla/mls long

[Tim Northover]

Hi Balaram,

Thanks for working on this. I think the code is mostly OK (which is a relief, otherwise ARM would already be broken). I've got a few small suggestions though:

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1738
@@ +1737,3 @@
+
+static SDValue SkipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
+  if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
----------------
Function names should start with a lower case letter (this isn't the only example).

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1845
@@ +1844,3 @@
+
+  // Legalize to a VMULL instruction
+  SDLoc DL(Op);
----------------
It's not called VMULL on AArch64.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1853
@@ +1852,3 @@
+           Op1.getValueType().is64BitVector() &&
+           "unexpected types for extended operands to VMULL");
+    return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
----------------
Ditto

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1856-1857
@@ +1855,4 @@
+  }
+  // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
+  // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
+  SDValue N00 = SkipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
----------------
Could you comment on which CPUs this is known to be beneficial for.

================
Comment at: test/CodeGen/AArch64/aarch64-smull.ll:287
@@ +286,3 @@
+define <2 x i64> @umull_extvec_v2i32_v2i64(<2 x i32> %arg) nounwind {
+; CHECK: umull_extvec_v2i32_v2i64
+; CHECK: umull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
----------------
CHECK-LABEL. It's also a good idea to include the label's ':' in the check line, otherwise you can match weird directives at the end of the function like 
    .size	umull_extvec_v2i32_v2i64, .Ltmp1-umull_extvec_v2i32_v2i64

http://reviews.llvm.org/D5589