[llvm] r218771 - Revert r216862 due to a performance regression
Jingyue Wu
jingyue at google.com
Wed Oct 1 08:22:14 PDT 2014
Author: jingyue
Date: Wed Oct 1 10:22:13 2014
New Revision: 218771
URL: http://llvm.org/viewvc/llvm-project?rev=218771&view=rev
Log:
Revert r216862 due to a performance regression
Reported by Alexey Volkov in PR21115
Removed:
llvm/trunk/test/CodeGen/NVPTX/machine-sink.ll
Modified:
llvm/trunk/lib/CodeGen/MachineSink.cpp
llvm/trunk/test/CodeGen/AArch64/arm64-atomic.ll
llvm/trunk/test/CodeGen/X86/loop-strength-reduce8.ll
Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=218771&r1=218770&r2=218771&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSink.cpp Wed Oct 1 10:22:13 2014
@@ -24,7 +24,6 @@
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
-#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
@@ -56,9 +55,8 @@ namespace {
class MachineSinking : public MachineFunctionPass {
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
- MachineRegisterInfo *MRI; // Machine register information
- MachineDominatorTree *DT; // Machine dominator tree
- MachinePostDominatorTree *PDT; // Machine post dominator tree
+ MachineRegisterInfo *MRI; // Machine register information
+ MachineDominatorTree *DT; // Machine dominator tree
MachineLoopInfo *LI;
const MachineBlockFrequencyInfo *MBFI;
AliasAnalysis *AA;
@@ -84,10 +82,8 @@ namespace {
MachineFunctionPass::getAnalysisUsage(AU);
AU.addRequired<AliasAnalysis>();
AU.addRequired<MachineDominatorTree>();
- AU.addRequired<MachinePostDominatorTree>();
AU.addRequired<MachineLoopInfo>();
AU.addPreserved<MachineDominatorTree>();
- AU.addPreserved<MachinePostDominatorTree>();
AU.addPreserved<MachineLoopInfo>();
if (UseBlockFreqInfo)
AU.addRequired<MachineBlockFrequencyInfo>();
@@ -255,7 +251,6 @@ bool MachineSinking::runOnMachineFunctio
TRI = TM.getSubtargetImpl()->getRegisterInfo();
MRI = &MF.getRegInfo();
DT = &getAnalysis<MachineDominatorTree>();
- PDT = &getAnalysis<MachinePostDominatorTree>();
LI = &getAnalysis<MachineLoopInfo>();
MBFI = UseBlockFreqInfo ? &getAnalysis<MachineBlockFrequencyInfo>() : nullptr;
AA = &getAnalysis<AliasAnalysis>();
@@ -474,6 +469,23 @@ static void collectDebugValues(MachineIn
}
}
+/// isPostDominatedBy - Return true if A is post dominated by B.
+static bool isPostDominatedBy(MachineBasicBlock *A, MachineBasicBlock *B) {
+
+ // FIXME - Use real post dominator.
+ if (A->succ_size() != 2)
+ return false;
+ MachineBasicBlock::succ_iterator I = A->succ_begin();
+ if (B == *I)
+ ++I;
+ MachineBasicBlock *OtherSuccBlock = *I;
+ if (OtherSuccBlock->succ_size() != 1 ||
+ *(OtherSuccBlock->succ_begin()) != B)
+ return false;
+
+ return true;
+}
+
/// isProfitableToSinkTo - Return true if it is profitable to sink MI.
bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
MachineBasicBlock *MBB,
@@ -485,8 +497,8 @@ bool MachineSinking::isProfitableToSinkT
return false;
// It is profitable if SuccToSinkTo does not post dominate current block.
- if (!PDT->dominates(SuccToSinkTo, MBB))
- return true;
+ if (!isPostDominatedBy(MBB, SuccToSinkTo))
+ return true;
// Check if only use in post dominated block is PHI instruction.
bool NonPHIUse = false;
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-atomic.ll?rev=218771&r1=218770&r2=218771&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-atomic.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-atomic.ll Wed Oct 1 10:22:13 2014
@@ -47,13 +47,13 @@ define i32 @fetch_and_nand(i32* %p) {
define i64 @fetch_and_nand_64(i64* %p) {
; CHECK-LABEL: fetch_and_nand_64:
+; CHECK: mov x[[ADDR:[0-9]+]], x0
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
-; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x0]
+; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
; CHECK: mvn w[[TMP_REG:[0-9]+]], w[[DEST_REG]]
; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], x[[TMP_REG]], #0xfffffffffffffff8
-; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
+; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
-; CHECK: mov x0, x[[DEST_REG]]
%val = atomicrmw nand i64* %p, i64 7 acq_rel
ret i64 %val
@@ -75,12 +75,12 @@ define i32 @fetch_and_or(i32* %p) {
define i64 @fetch_and_or_64(i64* %p) {
; CHECK: fetch_and_or_64:
+; CHECK: mov x[[ADDR:[0-9]+]], x0
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
-; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x0]
+; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], #0x7
-; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
+; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
-; CHECK: mov x0, [[DEST_REG]]
%val = atomicrmw or i64* %p, i64 7 monotonic
ret i64 %val
}
Removed: llvm/trunk/test/CodeGen/NVPTX/machine-sink.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/machine-sink.ll?rev=218770&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/machine-sink.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/machine-sink.ll (removed)
@@ -1,40 +0,0 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
-
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
-
- at scalar1 = internal addrspace(3) global float 0.000000e+00, align 4
- at scalar2 = internal addrspace(3) global float 0.000000e+00, align 4
-
-; We shouldn't sink mul.rn.f32 to BB %merge because BB %merge post-dominates
-; BB %entry. Over-sinking created more register pressure on this example. The
-; backend would sink the fmuls to BB %merge, but not the loads for being
-; conservative on sinking memory accesses. As a result, the loads and
-; the two fmuls would be separated to two basic blocks, causing two
-; cross-BB live ranges.
-define float @post_dominate(float %x, i1 %cond) {
-; CHECK-LABEL: post_dominate(
-entry:
- %0 = load float* addrspacecast (float addrspace(3)* @scalar1 to float*), align 4
- %1 = load float* addrspacecast (float addrspace(3)* @scalar2 to float*), align 4
-; CHECK: ld.shared.f32
-; CHECK: ld.shared.f32
- %2 = fmul float %0, %0
- %3 = fmul float %1, %2
-; CHECK-NOT: bra
-; CHECK: mul.rn.f32
-; CHECK: mul.rn.f32
- br i1 %cond, label %then, label %merge
-
-then:
- %z = fadd float %x, %x
- br label %then2
-
-then2:
- %z2 = fadd float %z, %z
- br label %merge
-
-merge:
- %y = phi float [ 0.0, %entry ], [ %z2, %then2 ]
- %w = fadd float %y, %3
- ret float %w
-}
Modified: llvm/trunk/test/CodeGen/X86/loop-strength-reduce8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/loop-strength-reduce8.ll?rev=218771&r1=218770&r2=218771&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/loop-strength-reduce8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/loop-strength-reduce8.ll Wed Oct 1 10:22:13 2014
@@ -1,9 +1,6 @@
; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
-; FIXME: The first two instructions, movl and addl, should have been combined to
-; "leal 16(%eax), %edx" by the backend (PR20776).
-; CHECK: movl %eax, %edx
-; CHECK: addl $16, %edx
+; CHECK: leal 16(%eax), %edx
; CHECK: align
; CHECK: addl $4, %edx
; CHECK: decl %ecx
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