[llvm] r218492 - Add the first backend support for on demand subtarget creation
Daniel Sanders
Daniel.Sanders at imgtec.com
Tue Sep 30 02:32:48 PDT 2014
Hi Eric,
> if (hasMips16Attr)
> FS += FS.empty() ? "+mips16" : ",+mips16";
> else if (hasNoMips16Attr)
> FS += FS.empty() ? "-mips16" : ",-mips16";
It looks like targets are going to end up using this kind of code a lot. Would
it make sense to switch the StringRef for a vector-like object at some point?
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of Eric Christopher
> Sent: 26 September 2014 02:44
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r218492 - Add the first backend support for on demand
> subtarget creation
>
> Author: echristo
> Date: Thu Sep 25 20:44:08 2014
> New Revision: 218492
>
> URL: http://llvm.org/viewvc/llvm-project?rev=218492&view=rev
> Log:
> Add the first backend support for on demand subtarget creation
> based on the Function. This is currently used to implement
> mips16 support in the mips backend via the existing module
> pass resetting the subtarget.
>
> Things to note:
>
> a) This involved running resetTargetOptions before creating a
> new subtarget so that code generation options like soft-float
> could be recognized when creating the new subtarget. This is
> to deal with initialization code in isel lowering that only
> paid attention to the initial value.
>
> b) Many of the existing testcases weren't using the soft-float
> feature correctly. I've corrected these based on the check
> values assuming that was the desired behavior.
>
> c) The mips port now pays attention to the target-cpu and
> target-features strings when generating code for a particular
> function. I've removed these from one function where the
> requested cpu and features didn't match the check lines in
> the testcase.
>
> Modified:
> llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> llvm/trunk/test/CodeGen/Mips/fp16instrinsmc.ll
> llvm/trunk/test/CodeGen/Mips/hfptrcall.ll
> llvm/trunk/test/CodeGen/Mips/nomips16.ll
> llvm/trunk/test/CodeGen/Mips/seleq.ll
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=218492&r1
> =218491&r2=218492&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Sep 25 20:44:08
> 2014
> @@ -56,7 +56,8 @@ MipsTargetMachine::MipsTargetMachine(con
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL, bool isLittle)
> : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
> - Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, this),
> + isLittle(isLittle), Subtarget(nullptr),
> + DefaultSubtarget(TT, CPU, FS, isLittle, this),
> NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-
> mips16",
> isLittle, this),
> Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
> @@ -83,20 +84,47 @@ MipselTargetMachine(const Target &T, Str
> CodeGenOpt::Level OL)
> : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
>
> +const MipsSubtarget *
> +MipsTargetMachine::getSubtargetImpl(const Function &F) const override {
> + AttributeSet FnAttrs = F.getAttributes();
> + Attribute CPUAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
> + Attribute FSAttr =
> + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
> +
> + std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
> + ? CPUAttr.getValueAsString().str()
> + : TargetCPU;
> + std::string FS = !FSAttr.hasAttribute(Attribute::None)
> + ? FSAttr.getValueAsString().str()
> + : TargetFS;
> + bool hasMips16Attr =
> + !FnAttrs.getAttribute(AttributeSet::FunctionIndex, "mips16")
> + .hasAttribute(Attribute::None);
> + bool hasNoMips16Attr =
> + !FnAttrs.getAttribute(AttributeSet::FunctionIndex, "nomips16")
> + .hasAttribute(Attribute::None);
> +
> + if (hasMips16Attr)
> + FS += FS.empty() ? "+mips16" : ",+mips16";
> + else if (hasNoMips16Attr)
> + FS += FS.empty() ? "-mips16" : ",-mips16";
> +
> + auto &I = SubtargetMap[CPU + FS];
> + if (!I) {
> + // This needs to be done before we create a new subtarget since any
> + // creation will depend on the TM and the code generation flags on the
> + // function that reside in TargetOptions.
> + resetTargetOptions(F);
> + I = make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, this);
> + }
> + return I.get();
> +}
> +
> void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
> DEBUG(dbgs() << "resetSubtarget\n");
> - AttributeSet FnAttrs = MF->getFunction()->getAttributes();
> - bool Mips16Attr = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
> "mips16");
> - bool NoMips16Attr =
> - FnAttrs.hasAttribute(AttributeSet::FunctionIndex, "nomips16");
> - assert(!(Mips16Attr && NoMips16Attr) &&
> - "mips16 and nomips16 specified on the same function");
> - if (Mips16Attr)
> - Subtarget = &Mips16Subtarget;
> - else if (NoMips16Attr)
> - Subtarget = &NoMips16Subtarget;
> - else
> - Subtarget = &DefaultSubtarget;
> +
> + Subtarget = const_cast<MipsSubtarget*>(getSubtargetImpl(MF-
> >getFunction()));
> MF->setSubtarget(Subtarget);
> return;
> }
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=218492&r1=2
> 18491&r2=218492&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Thu Sep 25 20:44:08
> 2014
> @@ -25,11 +25,14 @@ class formatted_raw_ostream;
> class MipsRegisterInfo;
>
> class MipsTargetMachine : public LLVMTargetMachine {
> + bool isLittle;
> MipsSubtarget *Subtarget;
> MipsSubtarget DefaultSubtarget;
> MipsSubtarget NoMips16Subtarget;
> MipsSubtarget Mips16Subtarget;
>
> + mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap;
> +
> public:
> MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef
> FS,
> const TargetOptions &Options, Reloc::Model RM,
> @@ -45,6 +48,8 @@ public:
> return &DefaultSubtarget;
> }
>
> + const MipsSubtarget *getSubtargetImpl(const Function &F) const
> override;
> +
> /// \brief Reset the subtarget for the Mips target.
> void resetSubtarget(MachineFunction *MF);
>
>
> Modified: llvm/trunk/test/CodeGen/Mips/fp16instrinsmc.ll
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/test/CodeGen/Mips/fp16instrinsmc.ll?rev=218492&r1=21
> 8491&r2=218492&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/test/CodeGen/Mips/fp16instrinsmc.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/fp16instrinsmc.ll Thu Sep 25 20:44:08
> 2014
> @@ -385,7 +385,7 @@ entry:
> ; Function Attrs: nounwind
> declare double @exp2(double) #0
>
> -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-
> elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-
> math"="false" "use-soft-float"="true" }
> +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-
> pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-
> math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> attributes #1 = { nounwind readnone "less-precise-fpmad"="false" "no-
> frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-
> math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
> "unsafe-fp-math"="false" "use-soft-float"="true" }
> attributes #2 = { nounwind readnone }
> attributes #3 = { nounwind }
>
> Modified: llvm/trunk/test/CodeGen/Mips/hfptrcall.ll
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/test/CodeGen/Mips/hfptrcall.ll?rev=218492&r1=218491&
> r2=218492&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/test/CodeGen/Mips/hfptrcall.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/hfptrcall.ll Thu Sep 25 20:44:08 2014
> @@ -118,8 +118,8 @@ entry:
>
> declare i32 @printf(i8*, ...) #1
>
> -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-
> elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-
> float"="true" }
> -attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-
> elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-
> float"="true" }
> +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-
> pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-
> math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-
> soft-float"="false" }
> +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-
> elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-
> float"="false" }
>
>
>
>
> Modified: llvm/trunk/test/CodeGen/Mips/nomips16.ll
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/test/CodeGen/Mips/nomips16.ll?rev=218492&r1=218491
> &r2=218492&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/test/CodeGen/Mips/nomips16.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/nomips16.ll Thu Sep 25 20:44:08 2014
> @@ -33,6 +33,6 @@ entry:
> ; CHECK: .end nofoo
>
>
> -attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "no-
> frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-
> math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
> "unsafe-fp-math"="false" "use-soft-float"="true" }
> -attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-
> elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
> "no-nans-fp-math"="false" "nomips16" "stack-protector-buffer-size"="8"
> "unsafe-fp-math"="false" "use-soft-float"="true" }
> +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "no-
> frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-
> math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
> "unsafe-fp-math"="false" "use-soft-float"="false" }
> +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-
> pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-
> math"="false" "no-nans-fp-math"="false" "nomips16" "stack-protector-
> buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
>
>
> Modified: llvm/trunk/test/CodeGen/Mips/seleq.ll
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/test/CodeGen/Mips/seleq.ll?rev=218492&r1=218491&r2
> =218492&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/test/CodeGen/Mips/seleq.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/seleq.ll Thu Sep 25 20:44:08 2014
> @@ -10,7 +10,7 @@
> @z3 = common global i32 0, align 4
> @z4 = common global i32 0, align 4
>
> -define void @calc_seleq() nounwind "target-cpu"="mips32" "target-
> features"="+o32,+mips32" {
> +define void @calc_seleq() nounwind {
> entry:
> %0 = load i32* @a, align 4
> %1 = load i32* @b, align 4
>
>
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