[PATCH] Fix TableGen -gen-disassembler output for certain bit field definitions.

[Tom Stellard]

On Fri, Sep 26, 2014 at 09:22:36AM -0700, Steve King wrote:
> On Fri, Sep 26, 2014 at 6:44 AM, Tom Stellard <tom at stellard.net> wrote:
> >
> > Tablegen has !shl and !srl operators, I think it would be good to add test
> > cases using those too.
> >
> 
> Hi Tom - How would you use the ! operators here?  The test verifies
> general cherry picking of bits from operand to instruction.  Shift
> wasn't the right term -- I should rename the test as
> "BitOffsetDecoder".

Hi Steve,

Sorry, I didn't look quite close enough at what you were doing.

In my head I was thinking it was something like:

def Inst {

  field bits<5> src;

  let Inst{2-0} = !srl(src, 2);
}

I think the patch is OK as is.

-Tom