[llvm] r218349 - R600/SI: Fix SIRegisterInfo::getPhysRegSubReg()

[Tom Stellard]

Author: tstellar
Date: Tue Sep 23 20:33:22 2014
New Revision: 218349

URL: http://llvm.org/viewvc/llvm-project?rev=218349&view=rev
Log:
R600/SI: Fix SIRegisterInfo::getPhysRegSubReg()

Correctly handle special registers: EXEC, EXEC_LO, EXEC_HI, VCC_LO,
VCC_HI, and M0.  The previous implementation would assertion fail
when passed these registers.

Modified:
    llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp?rev=218349&r1=218348&r2=218349&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp Tue Sep 23 20:33:22 2014
@@ -343,7 +343,6 @@ unsigned SIRegisterInfo::getPhysRegSubRe
         case 1: return AMDGPU::VCC_HI;
         default: llvm_unreachable("Invalid SubIdx for VCC");
       }
-      break;
 
   case AMDGPU::FLAT_SCR:
     switch (Channel) {
@@ -368,6 +367,16 @@ unsigned SIRegisterInfo::getPhysRegSubRe
     break;
   }
 
+  const TargetRegisterClass *RC = getPhysRegClass(Reg);
+  // 32-bit registers don't have sub-registers, so we can just return the
+  // Reg.  We need to have this check here, because the calculation below
+  // using getHWRegIndex() will fail with special 32-bit registers like
+  // VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
+  if (RC->getSize() == 4) {
+    assert(Channel == 0);
+    return Reg;
+  }
+
   unsigned Index = getHWRegIndex(Reg);
   return SubRC->getRegister(Index + Channel);
 }