[PATCH] Transform 3 operand instructions to 2 operand versions of the same instruction if first 2 register operands are the same for thumb1

[Ranjeet Singh]

Hi t.p.northover, rengolin,

This patch makes the ARM backend transform 3 operand instructions such as 'adds' to the 2 operand version of the same instruction if the first two register operands are the same e.g. 'adds r0, r0, #1' will is transformed to 'adds r0, #1'. Currently for some instructions such as  'adds' if you try to assemble 'adds r0, r0, #8'  for thumb v6m the assembler would throw an error message because the immediate cannot be encoded using 3 bits, the backend should be smart enough to transform the instruction to 'adds r0, #8'.

http://reviews.llvm.org/D5463

Files:
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  test/MC/ARM/thumb_rewrites.s
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