[PATCH] [ARM] [CodeGen] Do not emit intermediate register for zero FP immediate

[Sergey Dmitrouk]

Hi t.p.northover,

This updates check for double precision zero floating point constant to allow use of instruction with immediate value rather than temporary register.
Currently "a == 0.0", where "a" is of "double" type generates:

```
vmov.i32        d16, #0x0
vcmpe.f64       d0, d16
```

With this change it becomes:


```
vcmpe.f64        d0, #0
```

http://reviews.llvm.org/D5456

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  test/CodeGen/ARM/fpcmp-f64-neon-opt.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D5456.13970.patch
Type: text/x-patch
Size: 1475 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20140923/7c63a54e/attachment.bin>