[llvm] r218062 - Reverting NFC changes from r218050. Instead, the warning was disabled for GCC in r218059, so these changes are no longer required.
Eric Christopher
echristo at gmail.com
Thu Sep 18 16:47:05 PDT 2014
Thanks for the work either way. :)
-eric
On Thu, Sep 18, 2014 at 10:34 AM, Aaron Ballman <aaron at aaronballman.com> wrote:
> Author: aaronballman
> Date: Thu Sep 18 12:34:23 2014
> New Revision: 218062
>
> URL: http://llvm.org/viewvc/llvm-project?rev=218062&view=rev
> Log:
> Reverting NFC changes from r218050. Instead, the warning was disabled for GCC in r218059, so these changes are no longer required.
>
> Modified:
> llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.h
> llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h
> llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h
> llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
> llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h
> llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
> llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h
> llvm/trunk/lib/Target/X86/X86TargetMachine.h
> llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -31,7 +31,6 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL, bool IsLittleEndian);
>
> - using LLVMTargetMachine::getSubtargetImpl;
> const AArch64Subtarget *getSubtargetImpl() const override {
> return &Subtarget;
> }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -32,7 +32,6 @@ public:
> CodeGenOpt::Level OL,
> bool isLittle);
>
> - using LLVMTargetMachine::getSubtargetImpl;
> const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
>
> /// \brief Register ARM analysis passes with a pass manager.
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -31,7 +31,6 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL);
>
> - using LLVMTargetMachine::getSubtargetImpl;
> const HexagonSubtarget *getSubtargetImpl() const override {
> return &Subtarget;
> }
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -32,7 +32,6 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL);
>
> - using LLVMTargetMachine::getSubtargetImpl;
> const MSP430Subtarget *getSubtargetImpl() const override {
> return &Subtarget;
> }
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -39,7 +39,6 @@ public:
>
> void addAnalysisPasses(PassManagerBase &PM) override;
>
> - using LLVMTargetMachine::getSubtargetImpl;
> const MipsSubtarget *getSubtargetImpl() const override {
> if (Subtarget)
> return Subtarget;
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -35,7 +35,6 @@ public:
> const TargetOptions &Options, Reloc::Model RM,
> CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
>
> - using LLVMTargetMachine::getSubtargetImpl;
> const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
>
> ManagedStringPool *getManagedStrPool() const {
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -32,7 +32,6 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL);
>
> - using LLVMTargetMachine::getSubtargetImpl;
> const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
>
> // Pass Pipeline Configuration
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -33,8 +33,6 @@ public:
> StringRef CPU, TargetOptions Options, Reloc::Model RM,
> CodeModel::Model CM, CodeGenOpt::Level OL);
> ~AMDGPUTargetMachine();
> -
> - using LLVMTargetMachine::getSubtargetImpl;
> const AMDGPUSubtarget *getSubtargetImpl() const override {
> return &Subtarget;
> }
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -28,7 +28,6 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL, bool is64bit);
>
> - using LLVMTargetMachine::getSubtargetImpl;
> const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
>
> // Pass Pipeline Configuration
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -32,7 +32,6 @@ public:
> CodeGenOpt::Level OL);
>
> // Override TargetMachine.
> - using LLVMTargetMachine::getSubtargetImpl;
> const SystemZSubtarget *getSubtargetImpl() const override {
> return &Subtarget;
> }
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -31,8 +31,6 @@ public:
> StringRef CPU, StringRef FS, const TargetOptions &Options,
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL);
> -
> - using LLVMTargetMachine::getSubtargetImpl;
> const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
>
> /// \brief Register X86 analysis passes with a pass manager.
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=218062&r1=218061&r2=218062&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Thu Sep 18 12:34:23 2014
> @@ -27,7 +27,6 @@ public:
> Reloc::Model RM, CodeModel::Model CM,
> CodeGenOpt::Level OL);
>
> - using LLVMTargetMachine::getSubtargetImpl;
> const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; }
>
> // Pass Pipeline Configuration
>
>
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