[PATCH] R600/SI: Remove promotion of instructions to e64 forms.

[Tom Stellard]

On Mon, Sep 15, 2014 at 05:26:28PM +0000, Matt Arsenault wrote:
> Instructions are now generally selected to the e64 forms originally,
> and shrunk down later. Rename foldOperands to legalizeOperands,
> since that's really most of what it tries to do.
> 

LGTM.

> http://reviews.llvm.org/D5358
> 
> Files:
>   lib/Target/R600/SIISelLowering.cpp
>   lib/Target/R600/SIISelLowering.h

> Index: lib/Target/R600/SIISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/SIISelLowering.cpp
> +++ lib/Target/R600/SIISelLowering.cpp
> @@ -1709,10 +1709,10 @@
>    return false;
>  }
>  
> -/// \brief Try to fold the Nodes operands into the Node
> -SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
> -                                       SelectionDAG &DAG) const {
> -
> +/// \brief Try to commute instructions and insert copies in order to satisfy the
> +/// operand constraints.
> +SDNode *SITargetLowering::legalizeOperands(MachineSDNode *Node,
> +                                           SelectionDAG &DAG) const {
>    // Original encoding (either e32 or e64)
>    int Opcode = Node->getMachineOpcode();
>    const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
> @@ -1729,13 +1729,6 @@
>    assert(!DescRev || DescRev->getNumDefs() == NumDefs);
>    assert(!DescRev || DescRev->getNumOperands() == NumOps);
>  
> -  // e64 version if available, -1 otherwise
> -  int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
> -  const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
> -  int InputModifiers[3] = {0};
> -
> -  assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
> -
>    int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
>    bool HaveVSrc = false, HaveSSrc = false;
>  
> @@ -1767,7 +1760,6 @@
>  
>    // Second go over the operands and try to fold them
>    std::vector<SDValue> Ops;
> -  bool Promote2e64 = false;
>    for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
>         i != e && Op < NumOps; ++i, ++Op) {
>  
> @@ -1816,50 +1808,6 @@
>          continue;
>        }
>      }
> -
> -    if (Immediate)
> -      continue;
> -
> -    if (DescE64) {
> -      // Test if it makes sense to switch to e64 encoding
> -      unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
> -      if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
> -        continue;
> -
> -      int32_t TmpImm = -1;
> -      if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
> -          (!fitsRegClass(DAG, Ops[i], RegClass) &&
> -           fitsRegClass(DAG, Ops[1], OtherRegClass))) {
> -
> -        // Switch to e64 encoding
> -        Immediate = -1;
> -        Promote2e64 = true;
> -        Desc = DescE64;
> -        DescE64 = nullptr;
> -      }
> -    }
> -
> -    if (!DescE64 && !Promote2e64)
> -      continue;
> -    if (!Operand.isMachineOpcode())
> -      continue;
> -  }
> -
> -  if (Promote2e64) {
> -    std::vector<SDValue> OldOps(Ops);
> -    Ops.clear();
> -    bool HasModifiers = TII->hasModifiers(Desc->Opcode);
> -    for (unsigned i = 0; i < OldOps.size(); ++i) {
> -      // src_modifier
> -      if (HasModifiers)
> -        Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32));
> -      Ops.push_back(OldOps[i]);
> -    }
> -    // Add the modifier flags while promoting
> -    if (HasModifiers) {
> -      for (unsigned i = 0; i < 2; ++i)
> -        Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
> -    }
>    }
>  
>    // Add optional chain and glue
> @@ -1978,7 +1926,7 @@
>    if (TII->isMIMG(Node->getMachineOpcode()))
>      adjustWritemask(Node, DAG);
>  
> -  return foldOperands(Node, DAG);
> +  return legalizeOperands(Node, DAG);
>  }
>  
>  /// \brief Assign the register class depending on the number of
> Index: lib/Target/R600/SIISelLowering.h
> ===================================================================
> --- lib/Target/R600/SIISelLowering.h
> +++ lib/Target/R600/SIISelLowering.h
> @@ -50,7 +50,7 @@
>    void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
>                         unsigned RegClass, bool &ScalarSlotUsed) const;
>  
> -  SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
> +  SDNode *legalizeOperands(MachineSDNode *N, SelectionDAG &DAG) const;
>    void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
>    MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
>  

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