[llvm] r217736 - R600/SI: Fix broken check lines

Matt Arsenault Matthew.Arsenault at amd.com
Sun Sep 14 11:32:05 PDT 2014


Author: arsenm
Date: Sun Sep 14 13:32:05 2014
New Revision: 217736

URL: http://llvm.org/viewvc/llvm-project?rev=217736&view=rev
Log:
R600/SI: Fix broken check lines

Modified:
    llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll

Modified: llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll?rev=217736&r1=217735&r2=217736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll (original)
+++ llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll Sun Sep 14 13:32:05 2014
@@ -80,7 +80,7 @@ define void @store_lds_i64_align_4(i64 a
 }
 
 ; SI-LABEL: @store_lds_i64_align_4_with_offset
-; DS_WRITE_B32 v[{{[0-9]+}}], v[{{[0-9]+}}], v{{[0-9]}}, 0x9, 0x9
+; SI: DS_WRITE2_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, 0x8, 0x9
 ; SI: S_ENDPGM
 define void @store_lds_i64_align_4_with_offset(i64 addrspace(3)* %out) #0 {
   %ptr = getelementptr i64 addrspace(3)* %out, i32 4
@@ -90,7 +90,7 @@ define void @store_lds_i64_align_4_with_
 
 ; SI-LABEL: @store_lds_i64_align_4_with_split_offset
 ; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits
-; DS_WRITE_B32 v[{{[0-9]+}}], v[{{[0-9]+}}], v{{[0-9]}}, 0x0, 0x1
+; SI: DS_WRITE2_B32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]}}, 0x0, 0x1
 ; SI: S_ENDPGM
 define void @store_lds_i64_align_4_with_split_offset(i64 addrspace(3)* %out) #0 {
   %ptr = bitcast i64 addrspace(3)* %out to i32 addrspace(3)*





More information about the llvm-commits mailing list