[PATCH] [Power] Add a new feature flag for support of the sync instruction

Hal Finkel hfinkel at anl.gov
Thu Sep 11 18:27:07 PDT 2014


----- Original Message -----
> From: "Alex Rosenberg" <alexr at leftfield.org>
> To: morisset at google.com, jfb at chromium.org, hfinkel at anl.gov, wschmidt at linux.vnet.ibm.com
> Cc: alexr at leftfield.org, llvm-commits at cs.uiuc.edu
> Sent: Thursday, September 11, 2014 6:03:46 PM
> Subject: Re: [PATCH] [Power] Add a new feature flag for support of the sync instruction
> 
> 601 and others had sync.

As far as I can tell, the 440 and friends did not, and that's really what we're dealing with here. There was some divergence in earlier Book E processors, where they supported only msync (which is indeed equivalent to sync 0), but not any of the other sync forms. More recent Book E processors, such as the A2, support "sync" generally.

As far as I can tell, GNU binutils will accept "sync 0" when targeting the PPC 440 (or any PPC core for that matter), so we don't *need* to print the instruction as "msync" (assuming GNU binutils is what we care about). We could just make "msync" and assembler alias for "sync 0" and be done with it (while this does not match the letter of the ISA, it will certainly work well enough in practice). I'm okay with that solution.

 -Hal

> 
> It's somewhat bizarre to me to define new patterns and features to
> handle something that encodes to the same bit patterns.
> 
> I always assumed "generic" was for the purposes of generating code
> that ran on the maximum set of hardware and was scheduled in a way
> to do as well as possible without being specific. More or less, the
> kind of code that would be used by Mac developers.
> 
> http://reviews.llvm.org/D5316
> 
> 
> 

-- 
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory



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