[llvm] r217582 - [ARM] Add Thumb-2 code size optimization regression test for LSR (register).

Tilmann Scheller t.scheller at samsung.com
Thu Sep 11 03:45:50 PDT 2014


Author: tilmann
Date: Thu Sep 11 05:45:50 2014
New Revision: 217582

URL: http://llvm.org/viewvc/llvm-project?rev=217582&view=rev
Log:
[ARM] Add Thumb-2 code size optimization regression test for LSR (register).

Modified:
    llvm/trunk/test/CodeGen/ARM/thumb2-size-opt.ll

Modified: llvm/trunk/test/CodeGen/ARM/thumb2-size-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-size-opt.ll?rev=217582&r1=217581&r2=217582&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/thumb2-size-opt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/thumb2-size-opt.ll Thu Sep 11 05:45:50 2014
@@ -73,3 +73,12 @@ entry:
   %shr = lshr i32 %a, 13
   ret i32 %shr
 }
+
+define i32 @lsr-reg(i32 %a, i32 %b) nounwind readnone {
+; CHECK-LABEL: "lsr-reg":
+; CHECK: lsr.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
+; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}}  @ encoding: [{{0x..,0x..}}]
+entry:
+  %shr = lshr i32 %a, %b
+  ret i32 %shr
+}





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