[PATCH] R600/SI: Report offset in correct units for st64 DS instructions

[Tom Stellard]

On Tue, Sep 09, 2014 at 05:59:37PM +0000, Matt Arsenault wrote:
> Need to convert the 64 element offset into bytes, not just the element
> size like the normal case instructions.

LGTM.

>     
> Noticed by inspection. This can't be hit now because
> st64 instructions aren't emitted during instruction selection,
> and the post-RA scheduler isn't enabled.
> 
> http://reviews.llvm.org/D5274
> 
> Files:
>   lib/Target/R600/SIInstrInfo.cpp

> Index: lib/Target/R600/SIInstrInfo.cpp
> ===================================================================
> --- lib/Target/R600/SIInstrInfo.cpp
> +++ lib/Target/R600/SIInstrInfo.cpp
> @@ -161,6 +161,18 @@
>    return false;
>  }
>  
> +static bool isStride64(unsigned Opc) {
> +  switch (Opc) {
> +  case AMDGPU::DS_READ2ST64_B32:
> +  case AMDGPU::DS_READ2ST64_B64:
> +  case AMDGPU::DS_WRITE2ST64_B32:
> +  case AMDGPU::DS_WRITE2ST64_B64:
> +    return true;
> +  default:
> +    return false;
> +  }
> +}
> +
>  bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
>                                         unsigned &BaseReg, unsigned &Offset,
>                                         const TargetRegisterInfo *TRI) const {
> @@ -203,6 +215,9 @@
>          EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
>        }
>  
> +      if (isStride64(Opc))
> +        EltSize *= 64;
> +
>        const MachineOperand *AddrReg = getNamedOperand(*LdSt,
>                                                        AMDGPU::OpName::addr);
>        BaseReg = AddrReg->getReg();

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