[PATCH] Add experimental PBQP support
Arnaud A. de Grandmaison
arnaud.degrandmaison at arm.com
Sat Sep 6 08:08:09 PDT 2014
Hi Dave & Lang,
The AArch64 does not require extra constraints for the PBQP to work, but the AArch64/A57 benefits from setting additional constraints. On the A57, some sequence of operations will execute faster if some of their operands stays in even or odd registers. The Arch64FPLoadBalancing pass has been added to do some optimization there by permuting registers in the straight forward cases, whereas this can be solved generally and elegantly with the PBQP at register allocation time.
From: Lang Hames [mailto:lhames at gmail.com]
Sent: 06 September 2014 06:14
To: David Blaikie
Cc: Arnaud De Grandmaison; llvm-commits at cs.uiuc.edu; Tim Northover
Subject: Re: [PATCH] Add experimental PBQP support
Out-of-the-box PBQP knows about the standard constraints that CodeGen models. Any Target that works with the standard allocators (E.g. greedy) should also work with PBQP. I believe Arnaud's patch is an optimisation. (Arnaud - please correct me if I'm wrong and AArch64 did require extra constraints, but I don't think it should?)
On Fri, Sep 5, 2014 at 3:45 PM, David Blaikie <dblaikie at gmail.com> wrote:
This'll probably show how little I know about register allocation - but I thought Lang was telling me the other day that PBQP is essentially a drop/opt in for any architecture without having specific code for it (learning about the register set from the tablegen files and that was all it needed).
Is that the case? Is the extra code in your patch then tuning, essentially - making PBQP better than the baseline table-driven PBQP for AArch64/A57? Or is my understanding incorrect?
On Fri, Sep 5, 2014 at 1:49 PM, Arnaud A. de Grandmaison <arnaud.degrandmaison at arm.com> wrote:
I am currently investigating the benefits the PBQP register allocator could bring to the AArch64/A57.
This patch adds experimental support for PBQP. The PBQP is disabled by default, and can be enabled with the ‘–aarch64-pbqp’ command line option to llc when the cortex-a57 is in use.
I thought it would be a good thing to upstream this patch, as some other people in the community could be interested in experimenting with this allocator.
It passes all the tests (LNT, spec, …), but the performance of the generated code is not optimal yet. Expect some more patches in the coming days to improve the performance.
Arnaud A. de Grandmaison
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