[PATCH] R600/SI: Fix bug in SIInstrInfo::legalizeOpWithMove()

[Matt Arsenault]

On Sep 4, 2014, at 2:57 AM, Michel Dänzer <michel at daenzer.net> wrote:

> On 04.09.2014 06:38, Tom Stellard wrote:
>> We must constrain the destination register class of legalized operands
>> to a VGPR class or else the illegal operand may be folded back into
>> the instruction by the register coalescer.
>> 
>> This fixes a bug in add.ll that will be uncovered by future commits.
> 
> This patch currently breaks make check, see below. It's related to
> Matthew's 'Try to keep i32 mul on SALU' change, which also broke two
> piglit tests for me (more on that later). With that patch reverted, this
> patch seems to work fine.

This patch seems to be the correct fix for the problem I tried to fix in the mul patch. With the change that made to legalizeOpWithMove removed and this patch, all of these tests pass.

> 
> 
> FAIL: LLVM :: CodeGen/R600/mul.ll (3277 of 11533)
> ******************** TEST 'LLVM :: CodeGen/R600/mul.ll' FAILED ********************
> Script:
> --
> /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=redwood < /home/daenzer/src/llvm-git/llvm/test/CodeGen/R600/mul.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=EG /home/daenzer/src/llvm-git/llvm/test/CodeGen/R600/mul.ll -check-prefix=FUNC
> /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/llc -march=r600 -mcpu=verde -verify-machineinstrs < /home/daenzer/src/llvm-git/llvm/test/CodeGen/R600/mul.ll | /home/daenzer/src/llvm-git/llvm/build-amd64/Release+Debug+Asserts/bin/FileCheck -check-prefix=SI -check-prefix=FUNC /home/daenzer/src/llvm-git/llvm/test/CodeGen/R600/mul.ll
> --
> Exit Code: 1
> 
> Command Output (stderr):
> --
> 
> # After Register Allocation, before rewriter
> # Machine code for function v_mul64_sext_c: Post SSA
> Function Live Ins: %SGPR0_SGPR1 in %vreg0
> 
> 0B	BB#0: derived from LLVM BB %0
> 	    Live Ins: %SGPR0_SGPR1
> 16B		%vreg0<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg0
> 32B		%vreg23:sub0_sub1<def,read-undef> = S_LOAD_DWORDX2_IMM %vreg0, 9; mem:LD8[undef(addrspace=2)](nontemporal) SReg_128:%vreg23 SReg_64:%vreg0
> 48B		%vreg6:sub0_sub1<def,read-undef> = S_LOAD_DWORDX2_IMM %vreg0, 11; mem:LD8[undef(addrspace=2)](nontemporal) SReg_128:%vreg6 SReg_64:%vreg0
> 96B		%vreg6:sub2<def> = S_MOV_B32 -1; SReg_128:%vreg6
> 112B		%vreg6:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg6
> 192B		%vreg7<def> = BUFFER_LOAD_DWORD_OFFSET %vreg6, 0, 0, 0, 0, 0, %EXEC<imp-use>; mem:LD4[%in(addrspace=1)] VGPR_32:%vreg7 SReg_128:%vreg6
> 208B		%vreg31<def> = S_MOV_B32 80; VReg_32:%vreg31
> 224B		%vreg34:sub0<def,read-undef> = V_MUL_LO_I32 %vreg7, %vreg31, %EXEC<imp-use>; VReg_64:%vreg34 VGPR_32:%vreg7 VReg_32:%vreg31
> 256B		%vreg12<def> = S_MOV_B32 0; SReg_32:%vreg12
> 288B		%vreg34:sub1<def> = COPY %vreg12; VReg_64:%vreg34 SReg_32:%vreg12
> 304B		%vreg14<def> = S_MOV_B32 80; SReg_32:%vreg14
> 320B		%vreg53:sub0<def,read-undef> = V_MUL_HI_I32 %vreg7, %vreg14, %EXEC<imp-use>; VReg_64:%vreg53 VGPR_32:%vreg7 SReg_32:%vreg14
> 368B		%vreg53:sub1<def> = COPY %vreg12; VReg_64:%vreg53 SReg_32:%vreg12
> 384B		%vreg55<def> = V_LSHL_B64 %vreg53, 32, %EXEC<imp-use>; VReg_64:%vreg55,%vreg53
> 464B		%vreg47:sub0<def,read-undef> = V_OR_B32_e32 %vreg55:sub0, %vreg34:sub0, %EXEC<imp-use>; VReg_64:%vreg47,%vreg55,%vreg34
> 544B		%vreg47:sub1<def> = V_OR_B32_e32 %vreg55:sub1, %vreg34:sub1, %EXEC<imp-use>; VReg_64:%vreg47,%vreg55,%vreg34
> 656B		%vreg23:sub2<def> = COPY %vreg6:sub2; SReg_128:%vreg23,%vreg6
> 672B		%vreg23:sub3<def> = COPY %vreg6:sub3; SReg_128:%vreg23,%vreg6
> 704B		BUFFER_STORE_DWORDX2_OFFSET %vreg47, %vreg23, 0, 0, 0, 0, 0, %EXEC<imp-use>; mem:ST8[%out(addrspace=1)] VReg_64:%vreg47 SReg_128:%vreg23
> 720B		S_ENDPGM
> 
> # End machine code for function v_mul64_sext_c.
> 
> *** Bad machine code: Illegal virtual register for instruction ***
> - function:    v_mul64_sext_c
> - basic block: BB#0  (0x203de10) [0B;736B)
> - instruction: 208B	%vreg31<def> = S_MOV_B32 80; VReg_32:%vreg31
> - operand 0:   %vreg31<def>
> Expected a SReg_32 register, but got a VReg_32 register
> LLVM ERROR: Found 1 machine code errors.
> /home/daenzer/src/llvm-git/llvm/test/CodeGen/R600/mul.ll:83:15: error: expected string not found in input
> ; FUNC-LABEL: @v_mul64_sext_c:
>              ^
> <stdin>:134:16: note: scanning from here
> ;@mul64_sext_c:
>               ^
> <stdin>:142:2: note: possible intended match here
> .text
> ^
> 
> 
> 
> -- 
> Earthling Michel Dänzer            |                  http://www.amd.com
> Libre software enthusiast          |                Mesa and X developer
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