[PATCH] [AArch64] Generate CMN when comparing a short int with minus

Chad Rosier mcrosier at codeaurora.org
Wed Aug 27 08:49:39 PDT 2014


LGTM, once the new comments are addressed.  Any additional concerns can be addressed in post-commit reviews.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1084
@@ -1081,4 +1083,3 @@
   }
-
-  SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
-  AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
+  // Because the imm operand of ADDS is an unsigned immediate, in the range 0 to
+  // 4095.For i8 operand, the largest immediate is 255, it can be handled well.
----------------
Wording improvements:

The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.  For the i8 operand, the largest immediate is 255, so this can be easily encoded in the compare instruction.  For i16 operand, however, the largest immediate cannot be encoded in the compare.

Therefore, use a sign extending load and cmn to avoid materializing the -1 constant.  For example,

movz w1, #65535
ldrh w0, [x0, #0]
cmp w0, w1

=>

ldrsh w0, [x0, #0]
cmn w0, #1

Fundamental, we're relying on the property that (zext LHS) == (zext RHS) if and only if (sext LHS) == (sext RHS).  The checks are in place to ensure both the LHS and RHS are truely zero extended and to make sure the transformation is profitable.


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1097
@@ +1096,3 @@
+  if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
+    if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
+        isa<LoadSDNode>(LHS) &&
----------------
clang-format?

http://reviews.llvm.org/D4966






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