[PATCH] Improve Cost model for SLPVectorizer when we have a vector division by power of 2

Sanjay Patel spatel at rotateright.com
Thu Aug 21 10:19:56 PDT 2014


>>! In D4971#30, @spatel wrote: 
> I assume the intent of that flag is to say that the HW itself recognizes pow2div (signed or unsigned?) and can do it just as fast as a shift. 
> But I'm not aware of any vector ISA that even includes an integer division instruction.

Let me try to make my point here clearer: if there's no vector integer division instruction to use, then I think the value of isPow2DivCheap() is irrelevant; we have to implement division using shift(s) anyway.

I don't know if checking for the existence of a vector division instruction is available at this level of LLVM, so the point may be moot...or that could be added as another target feature flag?

http://reviews.llvm.org/D4971






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