[PATCH] [AArch32] Add support for FP rounding operations for ARMv8/AArch32.

[Saleem Abdulrasool]

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Comment at: lib/Target/ARM/ARMISelLowering.cpp:861
@@ +860,3 @@
+  if (Subtarget->hasV8Ops()) {
+    static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
+    for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
----------------
Whitespace between the MVT and closing brace.

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Comment at: lib/Target/ARM/ARMISelLowering.cpp:862
@@ +861,3 @@
+    static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
+    for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
+      MVT Ty = RoundingTypes[I];
----------------
It seems that range based loops would be nicer here.

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Comment at: lib/Target/ARM/ARMInstrVFP.td:694
@@ -693,3 +693,3 @@
 
-multiclass vrint_inst_zrx<string opc, bit op, bit op2> {
+multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
   def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
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Can there ever be the case that there is no desired pattern?  (e.g. does it make sense to have this be a default null_frag).

http://reviews.llvm.org/D4935