[llvm] r215753 - [FastISel][AArch64] Fix a latent bug in floating-point materialization.

[Juergen Ributzka]

Author: ributzka
Date: Fri Aug 15 13:55:55 2014
New Revision: 215753

URL: http://llvm.org/viewvc/llvm-project?rev=215753&view=rev
Log:
[FastISel][AArch64] Fix a latent bug in floating-point materialization.

The floating-point value positive zero (+0.0) is a valid immedate value
according to isFPImmLegal. As a result AArch64 FastISel went ahead and
used the immediate version of fmov to materialize the constant.

The problem is that the immediate version of fmov cannot encode an imediate for
postive zero. Instead a fmov from the zero register was supposed to be used in
this case.

This fix adds handling for this special case and uses fmov from the zero
register to materialize a positive zero (negative zeroes go to the constant
pool).

There is no test case for this, because this code is currently dead. It will be
enabled in a future commit and I will add a test case in a separate commit
after that.

This fixes <rdar://problem/18027157>.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=215753&r1=215752&r2=215753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Fri Aug 15 13:55:55 2014
@@ -230,10 +230,19 @@ unsigned AArch64FastISel::AArch64Materia
   // This checks to see if we can use FMOV instructions to materialize
   // a constant, otherwise we have to materialize via the constant pool.
   if (TLI.isFPImmLegal(Val, VT)) {
+    unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
+    // Positive zero (+0.0) has to be materialized with a fmov from the zero
+    // register, because the immediate version of fmov cannot encode zero.
+    if (Val.isPosZero()) {
+      unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
+      unsigned Opc = Is64Bit ? AArch64::FMOVDr : AArch64::FMOVSr;
+      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
+        .addReg(ZReg, getKillRegState(true));
+      return ResultReg;
+    }
     int Imm = Is64Bit ? AArch64_AM::getFP64Imm(Val)
                       : AArch64_AM::getFP32Imm(Val);
     unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi;
-    unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
       .addImm(Imm);
     return ResultReg;