[PATCH] ARM: Enable DP copy, load and store instructions for FPv4-SP

[Oliver Stannard]

The FPv4-SP floating-point unit is generally reffered to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers.

This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM.

http://reviews.llvm.org/D4907

Files:
  lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMCallingConv.h
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  lib/Target/ARM/ARMInstrVFP.td
  test/CodeGen/ARM/aapcs-hfa-code.ll
  test/CodeGen/ARM/darwin-eabi.ll
  test/CodeGen/Thumb2/aapcs.ll
  test/CodeGen/Thumb2/cortex-fp.ll
  test/CodeGen/Thumb2/float-cmp.ll
  test/CodeGen/Thumb2/float-intrinsics-double.ll
  test/CodeGen/Thumb2/float-intrinsics-float.ll
  test/CodeGen/Thumb2/float-ops.ll
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