[PATCH] Teach the AArch64 backend about half-precision floating point

[Oliver Stannard]

This patch makes half and vectors of half valid types for the AArch64 backend (half is known as f16 in the backend). This is mostly a case of adding f16 to all instruction selection patterns that can use it, but also adds some target-independent logic for promoting arithmetic operations to a wider floating-point type, and fixes up some AArch64 custom lowering which assumes that the smallest floating-point type is f32.

The motivation for this is that the ACLE (ARM C Language Extensions) allows __fp16 to be used as a function argument or return type, and it must be passed in floating-point registers. Previously, __fp16 was converted to i16, so the backend could not know to pass an __fp16 in a different register to a short.

http://reviews.llvm.org/D4879

Files:
  include/llvm/CodeGen/MachineValueType.h
  lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  lib/Target/AArch64/AArch64CallingConvention.td
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrFormats.td
  lib/Target/AArch64/AArch64InstrInfo.td
  lib/Target/AArch64/AArch64RegisterInfo.td
  test/CodeGen/AArch64/fp16-instructions.ll
  test/CodeGen/AArch64/fp16-intrinsics.ll
  test/CodeGen/AArch64/fp16-v4-instructions.ll
  test/CodeGen/AArch64/fp16-v8-instructions.ll
  test/CodeGen/AArch64/fp16-vector-shuffle.ll
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