[PATCH][AArch64] Enable sign check optimization by CSE
Sergey Dmitrouk
sdmitrouk at accesssoftek.com
Tue Aug 12 00:53:50 PDT 2014
Hello,
Hal, updated the comment, thanks.
Jiangning, it actually was correct as instruction type was
implicitly checked by parseCond(). I agree that explicit check is
much better and added it to findSuitableCompare() (was
"findCompareInstruction"), thanks.
Please find updated patch attached.
Best regards,
Sergey
On Mon, Aug 11, 2014 at 08:02:40PM -0700, Jiangning Liu wrote:
> Hi Sergey,
> I looked at your code again, and I believe this piece of code is
> incorrect,
> + A // Change immediate in comparison instruction (ADDS or SUBS).
> + A MachineInstr *MI = BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(),
> TII->get(Opc))
> + A A A .addOperand(CmpMI->getOperand(0))
> + A A A .addOperand(CmpMI->getOperand(1))
> + A A A .addImm(imm + correction)
> + A A A .addOperand(CmpMI->getOperand(3));
> + A CmpMI->eraseFromParent();
> +
> + A MachineInstr *BrMI = MI->getNextNode();
> +
> + A // Change condition in branch instruction.
> + A BuildMI(*MBB, BrMI, BrMI->getDebugLoc(), TII->get(AArch64::Bcc))
> + A A A .addImm(getAdjustedCmp(Cmp))
> + A A A .addOperand(BrMI->getOperand(1));
> + A BrMI->eraseFromParent();
> Here BrMI may not really be a branch instruction. You need to check this
> before enteringA adjustCmp.
> Thanks,
> -Jiangning
>
> 2014-08-12 8:04 GMT+08:00 Hal Finkel <hfinkel at anl.gov>:
>
> ----- Original Message -----
> > From: "Sergey Dmitrouk" <sdmitrouk at accesssoftek.com>
> > To: "Hal Finkel" <hfinkel at anl.gov>
> > Cc: "llvm-commits at cs.uiuc.edu for LLVM" <llvm-commits at cs.uiuc.edu>,
> "Jiangning Liu" <liujiangning1 at gmail.com>
> > Sent: Monday, August 11, 2014 7:31:47 AM
> > Subject: Re: [PATCH][AArch64] Enable sign check optimization by CSE
> >
> > Thanks, changed that part to:
> >
> > A A Due to the way selection DAG part that corresponds to switch
> case
> > A A is built,
>
> I recommend something like this: "As a result of the canonicalization
> employed by SelectionDAGBuilder::visitSwitchCase, DAGCombine, and other
> target-specific code, "
> >
> > Jiangning gave a nice overview of what really happens here:
> >
> > A A
> http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140721/227116.html
> >
> > I'm not sure whether CodeGenPrep is able to perform transformations
> > like
> > this one.
>
> Probably not. Based on Jiangning's explanation, the SDAG builder's
> canonicalization, and later code, is at fault here.
> A -Hal
> >
> > Cheers,
> > Sergey
> >
> > On Mon, Aug 11, 2014 at 04:56:25AM -0700, Hal Finkel wrote:
> > > ----- Original Message -----
> > > > From: "Sergey Dmitrouk" <sdmitrouk at accesssoftek.com>
> > > > To: "Hal Finkel" <hfinkel at anl.gov>
> > > > Cc: "llvm-commits at cs.uiuc.edu for LLVM"
> > > > <llvm-commits at cs.uiuc.edu>, "Jiangning Liu"
> > > > <liujiangning1 at gmail.com>
> > > > Sent: Monday, August 11, 2014 3:29:34 AM
> > > > Subject: Re: [PATCH][AArch64] Enable sign check optimization by
> > > > CSE
> > > >
> > > > Hi Hal,
> > > >
> > > > thanks for your comments. A getNexeNode() works. A I added more
> > > > verbose
> > > > comment at the top and examples in C after conditions. A I didn't
> > > > provide
> > > > more detailed examples for the later as it would repeat the top
> > > > comment.
> > > > Changes of instructions are quite straightforward once you get
> > > > the
> > > > idea
> > > > that value is changed by one and comparison inclusive/exclusive
> > > > type
> > > > is
> > > > switched. A Still can add it if you prefer, just don't want to
> > > > repeat
> > > > same information in several places.
> > >
> > > Thanks, these comments are much better.
> > >
> > > +// Unfortunately, due to they way other parts implemented,
> > > corresponding
> > >
> > > parts implemented -> parts are implemented
> > >
> > > Also, what other parts? Specifically, does this happen at the
> > > SelectionDAG stage or later? If not, I think this logic would be
> > > better in CodeGenPrep instead of here.
> > >
> > > A -Hal
> > >
> > > >
> > > > Updated patch is attached.
> > > >
> > > > Regards,
> > > > Sergey
> > > >
> > > > On Sun, Aug 10, 2014 at 05:32:57PM -0700, Hal Finkel wrote:
> > > > > Hi Sergey,
> > > > >
> > > > > + A MachineInstr *BrMI =
> > > > > &*std::next(MachineBasicBlock::iterator(MI));
> > > > >
> > > > > I think this can be: MachineInstr *BrMI = MI->getNextNode();
> > > > >
> > > > > + A A if (((HeadCmp == AArch64CC::GT && TrueCmp ==
> > > > > AArch64CC::LT) ||
> > > > > + A A A A A (HeadCmp == AArch64CC::LT && TrueCmp ==
> > > > > AArch64CC::GT))
> > > > > &&
> > > > > + A A A A std::abs(TrueImm - HeadImm) == 2) {
> > > > > + A A A adjustCmp(HeadCmpMI, HeadCmp);
> > > > > + A A A adjustCmp(TrueCmpMI, TrueCmp);
> > > > > + A A A Changed = true;
> > > > > + A A } else if (((HeadCmp == AArch64CC::GT && TrueCmp ==
> > > > > AArch64CC::GT) ||
> > > > > + A A A A A A A A (HeadCmp == AArch64CC::LT && TrueCmp ==
> > > > > AArch64CC::LT)) &&
> > > > > + A A A A A A A A std::abs(TrueImm - HeadImm) == 1) {
> > > > > + A A A if (HeadImm < TrueCmp) {
> > > > > + A A A A adjustCmp(HeadCmpMI, HeadCmp);
> > > > > + A A A } else {
> > > > > + A A A A adjustCmp(TrueCmpMI, TrueCmp);
> > > > > + A A A }
> > > > > + A A A Changed = true;
> > > > > + A A }
> > > > > + A }
> > > > >
> > > > > I think some comments here would be helpful here giving an
> > > > > example
> > > > > (before and after) for each of these cases. You provide an
> > > > > example
> > > > > in C form in your e-mail below, but no such example appears in
> > > > > the
> > > > > comments in the patch (and relating the example at the
> > > > > instruction
> > > > > level would be good too).
> > > > >
> > > > > Likewise, the comment at the top of the file should do at least
> > > > > as
> > > > > good a job at explaining what the pass does as your e-mail.
> > > > >
> > > > > Thanks,
> > > > > Hal
> > > > >
> > > > > ----- Original Message -----
> > > > > > From: "Sergey Dmitrouk" <sdmitrouk at accesssoftek.com>
> > > > > > To: "Jiangning Liu" <liujiangning1 at gmail.com>
> > > > > > Cc: "llvm-commits at cs.uiuc.edu for LLVM"
> > > > > > <llvm-commits at cs.uiuc.edu>
> > > > > > Sent: Sunday, August 10, 2014 1:25:38 PM
> > > > > > Subject: Re: [PATCH][AArch64] Enable sign check optimization
> > > > > > by
> > > > > > CSE
> > > > > >
> > > > > > Hi Jiangning,
> > > > > >
> > > > > > Please find attached patch that adds new pass. A It analyzes
> > > > > > branches
> > > > > > and
> > > > > > adjusts comparisons and conditions to make compare
> > > > > > instructions
> > > > > > look
> > > > > > the
> > > > > > same, so that CSE pass could remove them. A The patch is big,
> > > > > > but
> > > > > > half
> > > > > > of
> > > > > > it is test file (tried to make it simpler, but it leads to
> > > > > > generating
> > > > > > different assembly) and another half is the new pass, which
> > > > > > is
> > > > > > hard
> > > > > > to
> > > > > > break into smaller patches. A I think it demonstrates general
> > > > > > idea (comments in test has comments in C): for code like
> > > > > >
> > > > > > A A if ((a > 5 && b == c) || (a >= 5 && b == d)) {
> > > > > >
> > > > > > a is compared with 5 only once with the patch.
> > > > > >
> > > > > > Currently only SUBS and ADDS followed by b.?? are supported.
> > > > > > A If
> > > > > > this
> > > > > > patch is accepted, it should be possible to additionally:
> > > > > > A * cover TBNZ/TBZ, which are now used for checks like (x < 0)
> > > > > > A and
> > > > > > A A doesn't let my patch optimize this case; does it make
> > > > > > A A sense to
> > > > > > A A use
> > > > > > A A one CMP instruction instead of TBNZ followed by CMP?
> > > > > > A * handle other conditional instructions (e.g. CSET).
> > > > > >
> > > > > > Comments are welcome, not sure I did it all correctly. A Maybe
> > > > > > need to
> > > > > > add command-line option for the pass, TODO comments, debug
> > > > > > output,
> > > > > > statistics or rewrite some parts completely.
> > > > > >
> > > > > > Cheers,
> > > > > > Sergey
> > > > > >
> > > > > > _______________________________________________
> > > > > > llvm-commits mailing list
> > > > > > llvm-commits at cs.uiuc.edu
> > > > > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> > > > > >
> > > > >
> > > > > --
> > > > > Hal Finkel
> > > > > Assistant Computational Scientist
> > > > > Leadership Computing Facility
> > > > > Argonne National Laboratory
> > > >
> > >
> > > --
> > > Hal Finkel
> > > Assistant Computational Scientist
> > > Leadership Computing Facility
> > > Argonne National Laboratory
> >
>
> --
> Hal Finkel
> Assistant Computational Scientist
> Leadership Computing Facility
> Argonne National Laboratory
-------------- next part --------------
diff --git a/lib/Target/AArch64/AArch64.h b/lib/Target/AArch64/AArch64.h
index ebe3d33..2b65ae8 100644
--- a/lib/Target/AArch64/AArch64.h
+++ b/lib/Target/AArch64/AArch64.h
@@ -36,6 +36,7 @@ FunctionPass *createAArch64StorePairSuppressPass();
FunctionPass *createAArch64ExpandPseudoPass();
FunctionPass *createAArch64LoadStoreOptimizationPass();
ModulePass *createAArch64PromoteConstantPass();
+FunctionPass *createAArch64ConditionOptimizerPass();
FunctionPass *createAArch64AddressTypePromotionPass();
FunctionPass *createAArch64A57FPLoadBalancing();
/// \brief Creates an ARM-specific Target Transformation Info pass.
diff --git a/lib/Target/AArch64/AArch64ConditionOptimizer.cpp b/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
new file mode 100644
index 0000000..f9c74a7
--- /dev/null
+++ b/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
@@ -0,0 +1,308 @@
+//=- AArch64ConditionOptimizer.cpp - Remove useless comparisons for AArch64 -=//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass tries to make consecutive compares of values use same operands to
+// allow CSE pass to remove duplicated instructions. For this it analyzes
+// branches and adjusts comparisons with immediate values by converting:
+// * GE -> GT
+// * GT -> GE
+// * LT -> LE
+// * LE -> LT
+// and adjusting immediate values appropriately. It basically corrects two
+// immediate values towards each other to make them equal.
+//
+// Consider the following example in C:
+//
+// if ((a < 5 && ...) || (a > 5 && ...)) {
+// ~~~~~ ~~~~~
+// ^ ^
+// x y
+//
+// Here both "x" and "y" expressions compare "a" with "5". When "x" evaluates
+// to "false", "y" can just check flags set by the first comparison. As a
+// result of the canonicalization employed by
+// SelectionDAGBuilder::visitSwitchCase, DAGCombine, and other target-specific
+// code, assembly ends up in the form that is not CSE friendly:
+//
+// ...
+// cmp w8, #4
+// b.gt .LBB0_3
+// ...
+// .LBB0_3:
+// cmp w8, #6
+// b.lt .LBB0_6
+// ...
+//
+// Same assembly after the pass:
+//
+// ...
+// cmp w8, #5
+// b.ge .LBB0_3
+// ...
+// .LBB0_3:
+// cmp w8, #5 // <-- CSE pass removes this instruction
+// b.le .LBB0_6
+// ...
+//
+// Currently only SUBS and ADDS followed by b.?? are supported.
+//
+// TODO: maybe handle TBNZ/TBZ the same way as CMP when used instead for "a < 0"
+// TODO: handle other conditional instructions (e.g. CSET)
+//
+//===----------------------------------------------------------------------===//
+
+#include "AArch64.h"
+#include "llvm/ADT/DepthFirstIterator.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
+#include <cstdlib>
+
+using namespace llvm;
+
+#define DEBUG_TYPE "aarch64-condopt"
+
+STATISTIC(NumConditionsAdjusted, "Number of conditions adjusted");
+
+namespace {
+class AArch64ConditionOptimizer : public MachineFunctionPass {
+ const TargetInstrInfo *TII;
+ MachineDominatorTree *DomTree;
+
+public:
+ static char ID;
+ AArch64ConditionOptimizer() : MachineFunctionPass(ID) {}
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ void adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ MachineInstr *findSuitableCompare(MachineBasicBlock *MBB);
+ const char *getPassName() const override {
+ return "AArch64 Condition Optimizer";
+ }
+};
+} // end anonymous namespace
+
+char AArch64ConditionOptimizer::ID = 0;
+
+namespace llvm {
+void initializeAArch64ConditionOptimizerPass(PassRegistry &);
+}
+
+INITIALIZE_PASS_BEGIN(AArch64ConditionOptimizer, "aarch64-condopt",
+ "AArch64 CondOpt Pass", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
+INITIALIZE_PASS_END(AArch64ConditionOptimizer, "aarch64-condopt",
+ "AArch64 CondOpt Pass", false, false)
+
+FunctionPass *llvm::createAArch64ConditionOptimizerPass() {
+ return new AArch64ConditionOptimizer();
+}
+
+void AArch64ConditionOptimizer::getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<MachineDominatorTree>();
+ AU.addPreserved<MachineDominatorTree>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+}
+
+// Finds compare instruction that corresponds to supported types of branching.
+// Returns the instruction or nullptr on failures or detecting unsupported
+// instructions.
+MachineInstr *AArch64ConditionOptimizer::findSuitableCompare(
+ MachineBasicBlock *MBB) {
+ MachineBasicBlock::iterator I = MBB->getFirstTerminator();
+ if (I == MBB->end()) {
+ return nullptr;
+ }
+
+ if (I->getOpcode() != AArch64::Bcc) {
+ return nullptr;
+ }
+
+ // Now find the instruction controlling the terminator.
+ for (MachineBasicBlock::iterator B = MBB->begin(); I != B;) {
+ --I;
+ assert(!I->isTerminator() && "Spurious terminator");
+ switch (I->getOpcode()) {
+ // cmp is an alias for subs with a dead destination register.
+ case AArch64::SUBSWri:
+ case AArch64::SUBSXri:
+ // cmn is an alias for adds with a dead destination register.
+ case AArch64::ADDSWri:
+ case AArch64::ADDSXri:
+ return I;
+ }
+ }
+ DEBUG(dbgs() << "Flags not defined in BB#" << MBB->getNumber() << '\n');
+ return nullptr;
+}
+
+// Changes form of comparison inclusive <-> exclusive.
+static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) {
+ switch (Cmp) {
+ case AArch64CC::GT: return AArch64CC::GE;
+ case AArch64CC::GE: return AArch64CC::GT;
+ case AArch64CC::LT: return AArch64CC::LE;
+ case AArch64CC::LE: return AArch64CC::LT;
+ default:
+ llvm_unreachable("Unexpected condition code");
+ }
+}
+
+// Transforms GT -> GE, GE -> GT, LT -> LE, LE -> LT by updating comparison
+// operator and condition code.
+void AArch64ConditionOptimizer::adjustCmp(MachineInstr *CmpMI,
+ AArch64CC::CondCode Cmp) {
+ MachineBasicBlock *const MBB = CmpMI->getParent();
+ const int imm = (int)CmpMI->getOperand(2).getImm();
+
+ const unsigned Opc = CmpMI->getOpcode();
+
+ int correction = (Cmp == AArch64CC::GT) ? 1 : -1;
+ // Negate correction value for comparison with negative immediate (CMN).
+ if (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri) {
+ correction = -correction;
+ }
+
+ // Change immediate in comparison instruction (ADDS or SUBS).
+ MachineInstr *MI = BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc))
+ .addOperand(CmpMI->getOperand(0))
+ .addOperand(CmpMI->getOperand(1))
+ .addImm(imm + correction)
+ .addOperand(CmpMI->getOperand(3));
+ CmpMI->eraseFromParent();
+
+ MachineInstr *BrMI = MI->getNextNode();
+
+ // Change condition in branch instruction.
+ BuildMI(*MBB, BrMI, BrMI->getDebugLoc(), TII->get(AArch64::Bcc))
+ .addImm(getAdjustedCmp(Cmp))
+ .addOperand(BrMI->getOperand(1));
+ BrMI->eraseFromParent();
+
+ ++NumConditionsAdjusted;
+}
+
+// Parse a condition code returned by AnalyzeBranch, and compute the CondCode
+// corresponding to TBB.
+// Returns true if parsing was successful, otherwise false is returned.
+static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
+ // A normal br.cond simply has the condition code.
+ if (Cond[0].getImm() != -1) {
+ assert(Cond.size() == 1 && "Unknown Cond array format");
+ CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
+ return true;
+ }
+ return false;
+}
+
+bool AArch64ConditionOptimizer::runOnMachineFunction(MachineFunction &MF) {
+ DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
+ << "********** Function: " << MF.getName() << '\n');
+ TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
+ DomTree = &getAnalysis<MachineDominatorTree>();
+
+ bool Changed = false;
+
+ // Visit blocks in dominator tree pre-order. The pre-order enables multiple
+ // cmp-conversions from the same head block.
+ // Note that updateDomTree() modifies the children of the DomTree node
+ // currently being visited. The df_iterator supports that; it doesn't look at
+ // child_begin() / child_end() until after a node has been visited.
+ for (MachineDomTreeNode *I : depth_first(DomTree)) {
+ MachineBasicBlock *HBB = I->getBlock();
+
+ SmallVector<MachineOperand, 4> HeadCond;
+ MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
+ if (TII->AnalyzeBranch(*HBB, TBB, FBB, HeadCond)) {
+ continue;
+ }
+
+ // Equivalence check is to skip loops.
+ if (!TBB || TBB == HBB) {
+ continue;
+ }
+
+ SmallVector<MachineOperand, 4> TrueCond;
+ MachineBasicBlock *TBB_TBB = nullptr, *TBB_FBB = nullptr;
+ if (TII->AnalyzeBranch(*TBB, TBB_TBB, TBB_FBB, TrueCond)) {
+ continue;
+ }
+
+ MachineInstr *HeadCmpMI = findSuitableCompare(HBB);
+ if (!HeadCmpMI) {
+ continue;
+ }
+
+ MachineInstr *TrueCmpMI = findSuitableCompare(TBB);
+ if (!TrueCmpMI) {
+ continue;
+ }
+
+ AArch64CC::CondCode HeadCmp;
+ if (HeadCond.empty() || !parseCond(HeadCond, HeadCmp)) {
+ continue;
+ }
+
+ AArch64CC::CondCode TrueCmp;
+ if (TrueCond.empty() || !parseCond(TrueCond, TrueCmp)) {
+ continue;
+ }
+
+ const int HeadImm = (int)HeadCmpMI->getOperand(2).getImm();
+ const int TrueImm = (int)TrueCmpMI->getOperand(2).getImm();
+
+ DEBUG(dbgs() << "Head branch:\n");
+ DEBUG(dbgs() << "\tcondition: "
+ << AArch64CC::getCondCodeName(HeadCmp) << '\n');
+ DEBUG(dbgs() << "\timmediate: " << HeadImm << '\n');
+
+ DEBUG(dbgs() << "True branch:\n");
+ DEBUG(dbgs() << "\tcondition: "
+ << AArch64CC::getCondCodeName(TrueCmp) << '\n');
+ DEBUG(dbgs() << "\timmediate: " << TrueImm << '\n');
+
+ if (((HeadCmp == AArch64CC::GT && TrueCmp == AArch64CC::LT) ||
+ (HeadCmp == AArch64CC::LT && TrueCmp == AArch64CC::GT)) &&
+ std::abs(TrueImm - HeadImm) == 2) {
+ // This branch handles the following cases ({Imm} is the same on both
+ // sides):
+ // (a < {Imm} && ...) || (a > {Imm} && ...)
+ // (a > {Imm} && ...) || (a < {Imm} && ...)
+
+ adjustCmp(HeadCmpMI, HeadCmp);
+ adjustCmp(TrueCmpMI, TrueCmp);
+ Changed = true;
+ } else if (((HeadCmp == AArch64CC::GT && TrueCmp == AArch64CC::GT) ||
+ (HeadCmp == AArch64CC::LT && TrueCmp == AArch64CC::LT)) &&
+ std::abs(TrueImm - HeadImm) == 1) {
+ // This branch handles the following cases ({Imm} is the same on both
+ // sides):
+ // (a < {Imm} && ...) || (a <= {Imm} && ...)
+ // (a > {Imm} && ...) || (a >= {Imm} && ...)
+
+ if (HeadImm < TrueCmp) {
+ adjustCmp(HeadCmpMI, HeadCmp);
+ } else {
+ adjustCmp(TrueCmpMI, TrueCmp);
+ }
+ Changed = true;
+ }
+ }
+
+ return Changed;
+}
diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp
index d34be77..f719c63 100644
--- a/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -182,6 +182,7 @@ bool AArch64PassConfig::addInstSelector() {
}
bool AArch64PassConfig::addILPOpts() {
+ addPass(createAArch64ConditionOptimizerPass());
if (EnableCCMP)
addPass(createAArch64ConditionalCompares());
if (EnableMCR)
diff --git a/lib/Target/AArch64/CMakeLists.txt b/lib/Target/AArch64/CMakeLists.txt
index b1d8895..d5b54b7 100644
--- a/lib/Target/AArch64/CMakeLists.txt
+++ b/lib/Target/AArch64/CMakeLists.txt
@@ -27,6 +27,7 @@ add_llvm_target(AArch64CodeGen
AArch64ExpandPseudoInsts.cpp
AArch64FastISel.cpp
AArch64FrameLowering.cpp
+ AArch64ConditionOptimizer.cpp
AArch64ISelDAGToDAG.cpp
AArch64ISelLowering.cpp
AArch64InstrInfo.cpp
diff --git a/test/CodeGen/AArch64/combine-comparisons-by-cse.ll b/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
new file mode 100644
index 0000000..903a05c
--- /dev/null
+++ b/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
@@ -0,0 +1,229 @@
+; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s
+
+; marked as external to prevent possible optimizations
+ at a = external global i32
+ at b = external global i32
+ at c = external global i32
+ at d = external global i32
+
+; (a > 5 && b == c) || (a >= 5 && b == d)
+define i32 @combine_gt_ge_5() #0 {
+; CHECK-LABEL: combine_gt_ge_5
+; CHECK: cmp
+; CHECK: b.le
+; CHECK: ret
+; CHECK-NOT: cmp
+; CHECK: b.lt
+entry:
+ %0 = load i32* @a, align 4
+ %cmp = icmp sgt i32 %0, 5
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
+
+land.lhs.true: ; preds = %entry
+ %1 = load i32* @b, align 4
+ %2 = load i32* @c, align 4
+ %cmp1 = icmp eq i32 %1, %2
+ br i1 %cmp1, label %return, label %land.lhs.true3
+
+lor.lhs.false: ; preds = %entry
+ %cmp2 = icmp sgt i32 %0, 4
+ br i1 %cmp2, label %land.lhs.true3, label %if.end
+
+land.lhs.true3: ; preds = %lor.lhs.false, %land.lhs.true
+ %3 = load i32* @b, align 4
+ %4 = load i32* @d, align 4
+ %cmp4 = icmp eq i32 %3, %4
+ br i1 %cmp4, label %return, label %if.end
+
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false
+ br label %return
+
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]
+ ret i32 %retval.0
+}
+
+; (a > 5 && b == c) || (a < 5 && b == d)
+define i32 @combine_gt_lt_5() #0 {
+; CHECK-LABEL: combine_gt_lt_5
+; CHECK: cmp
+; CHECK: b.le
+; CHECK: ret
+; CHECK-NOT: cmp
+; CHECK: b.ge
+entry:
+ %0 = load i32* @a, align 4
+ %cmp = icmp sgt i32 %0, 5
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
+
+land.lhs.true: ; preds = %entry
+ %1 = load i32* @b, align 4
+ %2 = load i32* @c, align 4
+ %cmp1 = icmp eq i32 %1, %2
+ br i1 %cmp1, label %return, label %if.end
+
+lor.lhs.false: ; preds = %entry
+ %cmp2 = icmp slt i32 %0, 5
+ br i1 %cmp2, label %land.lhs.true3, label %if.end
+
+land.lhs.true3: ; preds = %lor.lhs.false
+ %3 = load i32* @b, align 4
+ %4 = load i32* @d, align 4
+ %cmp4 = icmp eq i32 %3, %4
+ br i1 %cmp4, label %return, label %if.end
+
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false, %land.lhs.true
+ br label %return
+
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]
+ ret i32 %retval.0
+}
+
+; (a < 5 && b == c) || (a <= 5 && b == d)
+define i32 @combine_lt_ge_5() #0 {
+; CHECK-LABEL: combine_lt_ge_5
+; CHECK: cmp
+; CHECK: b.ge
+; CHECK: ret
+; CHECK-NOT: cmp
+; CHECK: b.gt
+entry:
+ %0 = load i32* @a, align 4
+ %cmp = icmp slt i32 %0, 5
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
+
+land.lhs.true: ; preds = %entry
+ %1 = load i32* @b, align 4
+ %2 = load i32* @c, align 4
+ %cmp1 = icmp eq i32 %1, %2
+ br i1 %cmp1, label %return, label %land.lhs.true3
+
+lor.lhs.false: ; preds = %entry
+ %cmp2 = icmp slt i32 %0, 6
+ br i1 %cmp2, label %land.lhs.true3, label %if.end
+
+land.lhs.true3: ; preds = %lor.lhs.false, %land.lhs.true
+ %3 = load i32* @b, align 4
+ %4 = load i32* @d, align 4
+ %cmp4 = icmp eq i32 %3, %4
+ br i1 %cmp4, label %return, label %if.end
+
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false
+ br label %return
+
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]
+ ret i32 %retval.0
+}
+
+; (a < 5 && b == c) || (a > 5 && b == d)
+define i32 @combine_lt_gt_5() #0 {
+; CHECK-LABEL: combine_lt_gt_5
+; CHECK: cmp
+; CHECK: b.ge
+; CHECK: ret
+; CHECK-NOT: cmp
+; CHECK: b.le
+entry:
+ %0 = load i32* @a, align 4
+ %cmp = icmp slt i32 %0, 5
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
+
+land.lhs.true: ; preds = %entry
+ %1 = load i32* @b, align 4
+ %2 = load i32* @c, align 4
+ %cmp1 = icmp eq i32 %1, %2
+ br i1 %cmp1, label %return, label %if.end
+
+lor.lhs.false: ; preds = %entry
+ %cmp2 = icmp sgt i32 %0, 5
+ br i1 %cmp2, label %land.lhs.true3, label %if.end
+
+land.lhs.true3: ; preds = %lor.lhs.false
+ %3 = load i32* @b, align 4
+ %4 = load i32* @d, align 4
+ %cmp4 = icmp eq i32 %3, %4
+ br i1 %cmp4, label %return, label %if.end
+
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false, %land.lhs.true
+ br label %return
+
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]
+ ret i32 %retval.0
+}
+
+; (a > -5 && b == c) || (a < -5 && b == d)
+define i32 @combine_gt_lt_n5() #0 {
+; CHECK-LABEL: combine_gt_lt_n5
+; CHECK: cmn
+; CHECK: b.le
+; CHECK: ret
+; CHECK-NOT: cmn
+; CHECK: b.ge
+entry:
+ %0 = load i32* @a, align 4
+ %cmp = icmp sgt i32 %0, -5
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
+
+land.lhs.true: ; preds = %entry
+ %1 = load i32* @b, align 4
+ %2 = load i32* @c, align 4
+ %cmp1 = icmp eq i32 %1, %2
+ br i1 %cmp1, label %return, label %if.end
+
+lor.lhs.false: ; preds = %entry
+ %cmp2 = icmp slt i32 %0, -5
+ br i1 %cmp2, label %land.lhs.true3, label %if.end
+
+land.lhs.true3: ; preds = %lor.lhs.false
+ %3 = load i32* @b, align 4
+ %4 = load i32* @d, align 4
+ %cmp4 = icmp eq i32 %3, %4
+ br i1 %cmp4, label %return, label %if.end
+
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false, %land.lhs.true
+ br label %return
+
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]
+ ret i32 %retval.0
+}
+
+; (a < -5 && b == c) || (a > -5 && b == d)
+define i32 @combine_lt_gt_n5() #0 {
+; CHECK-LABEL: combine_lt_gt_n5
+; CHECK: cmn
+; CHECK: b.ge
+; CHECK: ret
+; CHECK-NOT: cmn
+; CHECK: b.le
+entry:
+ %0 = load i32* @a, align 4
+ %cmp = icmp slt i32 %0, -5
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false
+
+land.lhs.true: ; preds = %entry
+ %1 = load i32* @b, align 4
+ %2 = load i32* @c, align 4
+ %cmp1 = icmp eq i32 %1, %2
+ br i1 %cmp1, label %return, label %if.end
+
+lor.lhs.false: ; preds = %entry
+ %cmp2 = icmp sgt i32 %0, -5
+ br i1 %cmp2, label %land.lhs.true3, label %if.end
+
+land.lhs.true3: ; preds = %lor.lhs.false
+ %3 = load i32* @b, align 4
+ %4 = load i32* @d, align 4
+ %cmp4 = icmp eq i32 %3, %4
+ br i1 %cmp4, label %return, label %if.end
+
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false, %land.lhs.true
+ br label %return
+
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]
+ ret i32 %retval.0
+}
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