[PATCH] R600/SI: Custom lower CONCAT_VECTORS

Tom Stellard tom at stellard.net
Fri Aug 8 18:59:03 PDT 2014


On Thu, Aug 07, 2014 at 11:43:13AM -0700, Matt Arsenault wrote:
> On 08/07/2014 07:57 AM, Tom Stellard wrote:
> > This will lower them using register copies rather than loads and stores
> > to the stack.
> > ---
> >   lib/Target/R600/SIISelLowering.cpp  | 4 +++-
> >   test/CodeGen/R600/concat_vectors.ll | 3 +--
> >   2 files changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
> > index 2e982e2..16d66e5 100644
> > --- a/lib/Target/R600/SIISelLowering.cpp
> > +++ b/lib/Target/R600/SIISelLowering.cpp
> > @@ -196,10 +196,12 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
> >         case ISD::BITCAST:
> >         case ISD::EXTRACT_VECTOR_ELT:
> >         case ISD::INSERT_VECTOR_ELT:
> > -      case ISD::CONCAT_VECTORS:
> >         case ISD::INSERT_SUBVECTOR:
> >         case ISD::EXTRACT_SUBVECTOR:
> >           break;
> > +      case ISD::CONCAT_VECTORS:
> > +        setOperationAction(Op, VT, Custom);
> > +        break;
> >         default:
> >           setOperationAction(Op, VT, Expand);
> >           break;
> > diff --git a/test/CodeGen/R600/concat_vectors.ll b/test/CodeGen/R600/concat_vectors.ll
> > index 21c4af1..b8a0a5c 100644
> > --- a/test/CodeGen/R600/concat_vectors.ll
> > +++ b/test/CodeGen/R600/concat_vectors.ll
> > @@ -68,8 +68,7 @@ define void @test_concat_v4f32(<8 x float> addrspace(1)* %out, <4 x float> %a, <
> >   }
> >   
> >   ; FUNC-LABEL: @test_concat_v8f32
> > -; FIXME: This is currently being expanded with loads / stores to the stack.
> > -; FIXME-SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000
> > +; SI-NOT: S_MOV_B32 s{{[0-9]}}, 0x80f000
> >   define void @test_concat_v8f32(<16 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind {
> >     %concat = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
> >     store <16 x float> %concat, <16 x float> addrspace(1)* %out, align 64
> LGTM

r215270.
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