[PATCH] [X86] Allow atomic operations using immediates to avoid using a register

[Philip Reames]

I don't see an obvious errors in this change, but am not familiar with the areas you're touching in detail.  I believe the memory model aspects to be correct, but can not speak for the x86 backend details.  

It's worth noting that these instructions are specifically ordered *operations* not ordered *fences*.  There's no need to issue a StoreLoad barrier following the release since a Load from the same address is already ordered and Loads from other locations are unordered with respect to a release *operation*.  

I mention this only because I got confused reviewing the patch and it might be good to call it out in a comment.  It might also be worth adding a CHECK-NOT to ensure lack of lock prefix in case someone in the future gets this wrong.

http://reviews.llvm.org/D4796