[PATCH][X86] Split VALIGN out of X86ISD::PALINGR. Add masking VALINGD/Q

[Adam Nemet]

On Aug 5, 2014, at 2:48 AM, Demikhovsky, Elena <elena.demikhovsky at intel.com> wrote:

> Hi Adam,
> 
> You can commit all these changes. Robert will, probably, rewrite them to include SKX target.

I don’t think there should be a need to rewrite.  I think you can just drive the same multiclass with VR256X or VR128X as RC and that would hopefully work.  (I fixed up a few places before committing where I hard-coded VR512.)

Let me know if you disagree.  Obviously we want the two projects to go smoothly in parallel: the AVX512F completion and the BW/DQ/VL work.

Patches committed as r214885, r214886, r214887, r214888, r214889 and r214890.

Adam

> 
> -  Elena
> 
> 
> -----Original Message-----
> From: Adam Nemet [mailto:anemet at apple.com] 
> Sent: Tuesday, August 05, 2014 01:54
> To: Demikhovsky, Elena
> Cc: llvm-commits
> Subject: Re: [PATCH][X86] Split VALIGN out of X86ISD::PALINGR. Add masking VALINGD/Q
> 
> Apologies but the wrong version was sent out for the final patch in the series.  This should be the correct set now. 
> 
> On Aug 4, 2014, at 12:12 PM, Adam Nemet <anemet at apple.com> wrote:
> 
>> Hi,
>> 
>> I marked this patch X86 rather AVX512 because while its main purpose is to enable masking with valignd/q it also changes a bit how PALIGNR is handled.  I also had to increase X86_MAX_OPERANDS from 5 to 6 which is also an X86-wide change.
>> 
>> The flow of the patchset is essentially to do some refactoring on the related TD part to make the rest of the patches simpler, then split the DAG nodes PALINGR and VALIGN, then add the masking support along with the intrinsics.
>> 
>> See the individual patch files for more detailed explanation.
>> 
>> Please let me know if it looks good.  The clang counterpart to add the intrinsic header piece is ready to go to the CFE list.
>> 
>> Adam
>> 
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