[llvm] r214660 - R600/SI: Fix extra whitespace in asm str

[Matt Arsenault]

Author: arsenm
Date: Sun Aug  3 00:27:14 2014
New Revision: 214660

URL: http://llvm.org/viewvc/llvm-project?rev=214660&view=rev
Log:
R600/SI: Fix extra whitespace in asm str

This slipped in in r214467, so something like

V_MOV_B32_e32  v0, ... is now printed with 2 spaces
between the instruction name and first operand.

Added:
    llvm/trunk/test/CodeGen/R600/operand-spacing.ll
Modified:
    llvm/trunk/lib/Target/R600/SIInstrInfo.td

Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=214660&r1=214659&r2=214660&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.td Sun Aug  3 00:27:14 2014
@@ -442,7 +442,7 @@ class VOPProfile <list<ValueType> _ArgVT
   field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
                              HasModifiers>.ret;
 
-  field string Asm32 = "_e32 "#getAsm32<NumSrcArgs>.ret;
+  field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
   field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
 }
 

Added: llvm/trunk/test/CodeGen/R600/operand-spacing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/operand-spacing.ll?rev=214660&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/R600/operand-spacing.ll (added)
+++ llvm/trunk/test/CodeGen/R600/operand-spacing.ll Sun Aug  3 00:27:14 2014
@@ -0,0 +1,15 @@
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
+
+; Make sure there isn't an extra space between the instruction name and first operands.
+
+; SI-LABEL: @add_f32
+; SI-DAG: S_LOAD_DWORD [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
+; SI-DAG: S_LOAD_DWORD [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
+; SI: V_MOV_B32_e32 [[VREGB:v[0-9]+]], [[SREGB]]
+; SI: V_ADD_F32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]]
+; SI: BUFFER_STORE_DWORD [[RESULT]],
+define void @add_f32(float addrspace(1)* %out, float %a, float %b) {
+  %result = fadd float %a, %b
+  store float %result, float addrspace(1)* %out
+  ret void
+}