[PATCH] R600/SI: Implement getLdStBaseRegImmOfs for LDS

[Tom Stellard]

On Mon, Jul 28, 2014 at 11:59:01PM +0000, Matt Arsenault wrote:
> Use getNamedOperandIdx, implement for other address spaces
> 
> http://reviews.llvm.org/D4686
> 
> Files:
>   lib/Target/R600/SIInstrInfo.cpp
>   lib/Target/R600/SIInstrInfo.h
> 
> Index: lib/Target/R600/SIInstrInfo.cpp
> ===================================================================
> --- lib/Target/R600/SIInstrInfo.cpp
> +++ lib/Target/R600/SIInstrInfo.cpp
> @@ -32,6 +32,56 @@
>  // TargetInstrInfo callbacks
>  //===----------------------------------------------------------------------===//
>  
> +bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
> +                                       unsigned &BaseReg, unsigned &Offset,
> +                                       const TargetRegisterInfo *TRI) const {
> +  unsigned Opc = LdSt->getOpcode();
> +  if (isDS(Opc)) {
> +    int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
> +    if (OffsetIdx == -1) {
> +      // The 2 offset instructions use offset0 and offset1 instead. This
> +      // function only handles simple instructions with only a single offset, so
> +      // we ignore them.
> +      return false;
> +    }
> +
> +    int AddrIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr);

You can use getNamedOperand() to simplify the code.  It returns the
MachineOperand instead of the index.

Otherwise,
LGTM.
> +
> +    BaseReg = LdSt->getOperand(AddrIdx).getReg();
> +    Offset = LdSt->getOperand(OffsetIdx).getImm();
> +    return true;
> +  }
> +
> +  if (isMUBUF(Opc) || isMTBUF(Opc)) {
> +    if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
> +      return false;
> +
> +    int VaddrIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr);
> +    if (VaddrIdx == -1)
> +      return false;
> +
> +    int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
> +
> +    BaseReg = LdSt->getOperand(VaddrIdx).getReg();
> +    Offset = LdSt->getOperand(OffsetIdx).getImm();
> +    return true;
> +  }
> +
> +  if (isSMRD(Opc)) {
> +    int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
> +    if (OffsetIdx == -1)
> +      return false;
> +
> +    int SBaseIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase);
> +
> +    BaseReg = LdSt->getOperand(SBaseIdx).getReg();
> +    Offset = LdSt->getOperand(OffsetIdx).getImm();
> +    return true;
> +  }
> +
> +  return false;
> +}
> +
>  void
>  SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
>                           MachineBasicBlock::iterator MI, DebugLoc DL,
> Index: lib/Target/R600/SIInstrInfo.h
> ===================================================================
> --- lib/Target/R600/SIInstrInfo.h
> +++ lib/Target/R600/SIInstrInfo.h
> @@ -62,6 +62,10 @@
>      return RI;
>    }
>  
> +  bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
> +                            unsigned &BaseReg, unsigned &Offset,
> +                            const TargetRegisterInfo *TRI) const final;
> +
>    void copyPhysReg(MachineBasicBlock &MBB,
>                     MachineBasicBlock::iterator MI, DebugLoc DL,
>                     unsigned DestReg, unsigned SrcReg,

> Index: lib/Target/R600/SIInstrInfo.cpp
> ===================================================================
> --- lib/Target/R600/SIInstrInfo.cpp
> +++ lib/Target/R600/SIInstrInfo.cpp
> @@ -32,6 +32,56 @@
>  // TargetInstrInfo callbacks
>  //===----------------------------------------------------------------------===//
>  
> +bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
> +                                       unsigned &BaseReg, unsigned &Offset,
> +                                       const TargetRegisterInfo *TRI) const {
> +  unsigned Opc = LdSt->getOpcode();
> +  if (isDS(Opc)) {
> +    int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
> +    if (OffsetIdx == -1) {
> +      // The 2 offset instructions use offset0 and offset1 instead. This
> +      // function only handles simple instructions with only a single offset, so
> +      // we ignore them.
> +      return false;
> +    }
> +
> +    int AddrIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr);
> +
> +    BaseReg = LdSt->getOperand(AddrIdx).getReg();
> +    Offset = LdSt->getOperand(OffsetIdx).getImm();
> +    return true;
> +  }
> +
> +  if (isMUBUF(Opc) || isMTBUF(Opc)) {
> +    if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
> +      return false;
> +
> +    int VaddrIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr);
> +    if (VaddrIdx == -1)
> +      return false;
> +
> +    int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
> +
> +    BaseReg = LdSt->getOperand(VaddrIdx).getReg();
> +    Offset = LdSt->getOperand(OffsetIdx).getImm();
> +    return true;
> +  }
> +
> +  if (isSMRD(Opc)) {
> +    int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
> +    if (OffsetIdx == -1)
> +      return false;
> +
> +    int SBaseIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase);
> +
> +    BaseReg = LdSt->getOperand(SBaseIdx).getReg();
> +    Offset = LdSt->getOperand(OffsetIdx).getImm();
> +    return true;
> +  }
> +
> +  return false;
> +}
> +
>  void
>  SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
>                           MachineBasicBlock::iterator MI, DebugLoc DL,
> Index: lib/Target/R600/SIInstrInfo.h
> ===================================================================
> --- lib/Target/R600/SIInstrInfo.h
> +++ lib/Target/R600/SIInstrInfo.h
> @@ -62,6 +62,10 @@
>      return RI;
>    }
>  
> +  bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
> +                            unsigned &BaseReg, unsigned &Offset,
> +                            const TargetRegisterInfo *TRI) const final;
> +
>    void copyPhysReg(MachineBasicBlock &MBB,
>                     MachineBasicBlock::iterator MI, DebugLoc DL,
>                     unsigned DestReg, unsigned SrcReg,

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