[PATCH] ARM: Tighten up disassembling of MSR mask for M-class

[Petr Pavlu]

Hi James,

Thank you for reviewing this. I am attaching a new patch to address your comments.

> ================
> Comment at: lib/Target/ARM/Disassembler/ARMDisassembler.cpp:4009
> @@ +4008,3 @@
> +    // Validate the 2-bit mask value in MSR for v7m.
> +    if ((FeatureBits & ARM::HasV7Ops) && Inst.getOpcode() == ARM::t2MSR_M) {
> +      unsigned Mask = Val >> 10;
> ----------------
> MSR only appears to have one encoding. What are you trying to achieve by checking the opcode here?

This code path (function DecodeMSRMask()) is also used for the MRS instruction.
In that case, the 2-bit mask value will be always zero (because the MRS
instruction has no mask) and no mask validation should be done. 

Thanks,
Petr

http://reviews.llvm.org/D4694

Files:
  lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
  test/MC/Disassembler/ARM/thumb-MSR-MClass.txt
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