[PATCH] [mips] Don't use odd-numbered single precision registers for fastcc calling convention if -mno-odd-spreg is used.
daniel.sanders at imgtec.com
Sat Jul 26 07:31:34 PDT 2014
LGTM, with a nit
I'll merge it to the branch once it's committed since it fixes the last of the MIPS32r6/MIPS64r6 test-suite failures.
Comment at: test/CodeGen/Mips/fastcc.ll:300-302
@@ +299,5 @@
+; NOODDSPREG-DAG: lw $[[R0:[0-9]+]], %got(gfa10)($[[GP]])
+; For some reason the expression $[[F0:f[0-9]*]] for even float registers
+; doesn't work here (it works below in callee2), so I just enumerated the
+; NOODDSPREG-DAG: lwc1 $[[F0:f20|f22|f24|f26|f28|f30]], 0($[[R0]])
It's because FileCheck scans ahead for ']]' which leaves the pattern as 'f[0-9]*[02468'. I usually work around it using a '+' like so:
I can't explain why the other one works though. Triple ']' has never worked correctly for me.
Comment at: test/CodeGen/Mips/fastcc.ll:357
@@ +356,3 @@
+; NOODDSPREG-DAG: lw $[[R0:[0-9]+]], %got(gf10)($[[GP]])
+; NOODDSPREG-DAG: lwc1 $[[F0:f[0-9]*]], [[OFFSET]]($sp)
+; NOODDSPREG-DAG: swc1 $[[F0]], 0($[[R0]])
Nit: Change the ']]]' to ']+]]' since we don't understand why this particular case works when all other cases of ']]]' we've encountered result in invalid regexes
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