[llvm] r213750 - [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRB instructions.

[Tilmann Scheller]

Discussed this on IRC with James and Tim, we concluded that this is the
right behavior (since the assembler rejects the unpredictable instruction
and the disassembler won't error out on the instruction).

At some point we might consider adding a "demote to warning" flag for people
who insist on assembling encodable but unpredictable instructions.

Regards,

Tilmann

-----Original Message-----
From: James Molloy [mailto:james.molloy at arm.com] 
Sent: Wednesday, July 23, 2014 3:58 PM
To: 'Tilmann Scheller'; llvm-commits at cs.uiuc.edu
Subject: RE: [llvm] r213750 - [ARM] Make the assembler reject unpredictable
pre/post-indexed ARM STRB instructions.

Hi Tilmann,

I don't think this is correct. The behaviour is unpredictable, not
unencodable. Therefore, the assembler should return SoftFail rather than
Fail (this is what SoftFail was introduced for), and it should end up as a
warning not an error.

The rationale behind this is that if an encoding is representable as an
instruction, it should be disassembled/decoded. Obvious examples include
running objdump on an image that came from another compiler/assembler - we
don't want objdump to crash, we want it to report a problem with an
instruction and to continue.

Please revert this change and change to a warning, or our internal MC hammer
testing suite will fail overnight.

Cheers,

James

> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits- 
> bounces at cs.uiuc.edu] On Behalf Of Tilmann Scheller
> Sent: 23 July 2014 14:04
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r213750 - [ARM] Make the assembler reject 
> unpredictable pre/post-indexed ARM STRB instructions.
> 
> Author: tilmann
> Date: Wed Jul 23 08:03:47 2014
> New Revision: 213750
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=213750&view=rev
> Log:
> [ARM] Make the assembler reject unpredictable pre/post-indexed ARM 
> STRB instructions.
> 
> The ARM ARM prohibits STRB instructions with writeback into the source 
> register. With this commit this constraint is now enforced and we stop 
> assembling STRB instructions with unpredictable behavior.
> 
> Modified:
>     llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>     llvm/trunk/test/MC/ARM/diagnostics.s
> 
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=21375
> 0&r1
> =213749&r2=213750&view=diff
> ======================================================================
> ====
> ====
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jul 23
> 08:03:47 2014
> @@ -5731,7 +5731,11 @@ bool ARMAsmParser::validateInstruction(M
>    case ARM::STR_PRE_IMM:
>    case ARM::STR_PRE_REG:
>    case ARM::STR_POST_IMM:
> -  case ARM::STR_POST_REG: {
> +  case ARM::STR_POST_REG:
> +  case ARM::STRB_PRE_IMM:
> +  case ARM::STRB_PRE_REG:
> +  case ARM::STRB_POST_IMM:
> +  case ARM::STRB_POST_REG: {
>      // Rt must be different from Rn.
>      const unsigned Rt = MRI-
> >getEncodingValue(Inst.getOperand(1).getReg());
>      const unsigned Rn = MRI-
> >getEncodingValue(Inst.getOperand(2).getReg());
> 
> Modified: llvm/trunk/test/MC/ARM/diagnostics.s
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=213750&r1=213749&r2=2
> 1375
> 0&view=diff
> ======================================================================
> ====
> ====
> --- llvm/trunk/test/MC/ARM/diagnostics.s (original)
> +++ llvm/trunk/test/MC/ARM/diagnostics.s Wed Jul 23 08:03:47 2014
> @@ -496,6 +496,10 @@ foo2:
>          str r0, [r0, r1]!
>          str r0, [r0], #4
>          str r0, [r0], r1
> +        strb r0, [r0, #1]!
> +        strb r0, [r0, r1]!
> +        strb r0, [r0], #1
> +        strb r0, [r0], r1
>  @ CHECK-ERRORS: error: source register and base register can't be 
> identical  @ CHECK-ERRORS: str r0, [r0, #4]!
>  @ CHECK-ERRORS:         ^
> @@ -508,3 +512,15 @@ foo2:
>  @ CHECK-ERRORS: error: source register and base register can't be 
> identical  @ CHECK-ERRORS: str r0, [r0], r1
>  @ CHECK-ERRORS:         ^
> +@ CHECK-ERRORS: error: source register and base register can't be
> identical
> +@ CHECK-ERRORS: strb r0, [r0, #1]!
> +@ CHECK-ERRORS:          ^
> +@ CHECK-ERRORS: error: source register and base register can't be
> identical
> +@ CHECK-ERRORS: strb r0, [r0, r1]!
> +@ CHECK-ERRORS:          ^
> +@ CHECK-ERRORS: error: source register and base register can't be
> identical
> +@ CHECK-ERRORS: strb r0, [r0], #1
> +@ CHECK-ERRORS:          ^
> +@ CHECK-ERRORS: error: source register and base register can't be
> identical
> +@ CHECK-ERRORS: strb r0, [r0], r1
> +@ CHECK-ERRORS:          ^
> 
> 
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