[llvm] r213703 - [AArch64] Use CHECK-LABEL in ARM64 ABI unit tests.
Juergen Ributzka
juergen at apple.com
Tue Jul 22 16:14:54 PDT 2014
Author: ributzka
Date: Tue Jul 22 18:14:54 2014
New Revision: 213703
URL: http://llvm.org/viewvc/llvm-project?rev=213703&view=rev
Log:
[AArch64] Use CHECK-LABEL in ARM64 ABI unit tests.
Modified:
llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll
llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll?rev=213703&r1=213702&r2=213703&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll Tue Jul 22 18:14:54 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -debug -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s
+; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s
; RUN: llc < %s -O0 | FileCheck -check-prefix=FAST %s
; REQUIRES: asserts
target triple = "arm64-apple-darwin"
@@ -42,7 +42,7 @@ entry:
define i32 @i8i16caller() nounwind readnone {
entry:
-; CHECK: i8i16caller
+; CHECK-LABEL: i8i16caller
; The 8th, 9th, 10th and 11th arguments are passed at sp, sp+2, sp+4, sp+5.
; They are i8, i16, i8 and i8.
; CHECK-DAG: strb {{w[0-9]+}}, [sp, #5]
@@ -50,7 +50,7 @@ entry:
; CHECK-DAG: strh {{w[0-9]+}}, [sp, #2]
; CHECK-DAG: strb {{w[0-9]+}}, [sp]
; CHECK: bl
-; FAST: i8i16caller
+; FAST-LABEL: i8i16caller
; FAST: strb {{w[0-9]+}}, [sp]
; FAST: strh {{w[0-9]+}}, [sp, #2]
; FAST: strb {{w[0-9]+}}, [sp, #4]
@@ -64,7 +64,7 @@ entry:
; rdar://12651543
define double @circle_center([2 x float] %a) nounwind ssp {
%call = tail call double @ext([2 x float] %a) nounwind
-; CHECK: circle_center
+; CHECK-LABEL: circle_center
; CHECK: bl
ret double %call
}
@@ -75,9 +75,9 @@ declare double @ext([2 x float])
; A double argument will be passed on stack, so vecotr should be at sp+16.
define double @fixed_4i(<4 x i32>* nocapture %in) nounwind {
entry:
-; CHECK: fixed_4i
+; CHECK-LABEL: fixed_4i
; CHECK: str [[REG_1:q[0-9]+]], [sp, #16]
-; FAST: fixed_4i
+; FAST-LABEL: fixed_4i
; FAST: sub sp, sp, #64
; FAST: mov x[[ADDR:[0-9]+]], sp
; FAST: str [[REG_1:q[0-9]+]], [x[[ADDR]], #16]
@@ -93,7 +93,7 @@ declare double @args_vec_4i(double, <4 x
define void @test1(float %f1, double %d1, double %d2, double %d3, double %d4,
double %d5, double %d6, double %d7, double %d8, i32 %i) nounwind ssp {
entry:
-; CHECK: test1
+; CHECK-LABEL: test1
; CHECK: ldr [[REG_1:d[0-9]+]], [sp]
; CHECK: scvtf [[REG_2:s[0-9]+]], w0
; CHECK: fadd s0, [[REG_2]], s0
@@ -110,7 +110,7 @@ entry:
define void @test2(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
i32 %i7, i32 %i8, i32 %i9, float %d1) nounwind ssp {
entry:
-; CHECK: test2
+; CHECK-LABEL: test2
; CHECK: scvtf [[REG_2:s[0-9]+]], w0
; CHECK: fadd s0, [[REG_2]], s0
; CHECK: ldr [[REG_1:s[0-9]+]], [sp]
@@ -129,9 +129,9 @@ entry:
; Check alignment on stack for v64, f64, i64, f32, i32.
define double @test3(<2 x i32>* nocapture %in) nounwind {
entry:
-; CHECK: test3
+; CHECK-LABEL: test3
; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
-; FAST: test3
+; FAST-LABEL: test3
; FAST: sub sp, sp, #32
; FAST: mov x[[ADDR:[0-9]+]], sp
; FAST: str [[REG_1:d[0-9]+]], [x[[ADDR]], #8]
@@ -146,7 +146,7 @@ declare double @args_vec_2i(double, <2 x
define double @test4(double* nocapture %in) nounwind {
entry:
-; CHECK: test4
+; CHECK-LABEL: test4
; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
; CHECK: str [[REG_2:w[0-9]+]], [sp]
; CHECK: orr w0, wzr, #0x3
@@ -161,7 +161,7 @@ declare double @args_f64(double, double,
define i64 @test5(i64* nocapture %in) nounwind {
entry:
-; CHECK: test5
+; CHECK-LABEL: test5
; CHECK: strb [[REG_3:w[0-9]+]], [sp, #16]
; CHECK: str [[REG_1:x[0-9]+]], [sp, #8]
; CHECK: str [[REG_2:w[0-9]+]], [sp]
@@ -175,7 +175,7 @@ declare i64 @args_i64(i64, i64, i64, i64
define i32 @test6(float* nocapture %in) nounwind {
entry:
-; CHECK: test6
+; CHECK-LABEL: test6
; CHECK: strb [[REG_2:w[0-9]+]], [sp, #8]
; CHECK: str [[REG_1:s[0-9]+]], [sp, #4]
; CHECK: strh [[REG_3:w[0-9]+]], [sp]
@@ -192,7 +192,7 @@ declare i32 @args_f32(i32, i32, i32, i32
define i32 @test7(i32* nocapture %in) nounwind {
entry:
-; CHECK: test7
+; CHECK-LABEL: test7
; CHECK: strb [[REG_2:w[0-9]+]], [sp, #8]
; CHECK: str [[REG_1:w[0-9]+]], [sp, #4]
; CHECK: strh [[REG_3:w[0-9]+]], [sp]
@@ -206,13 +206,13 @@ declare i32 @args_i32(i32, i32, i32, i32
define i32 @test8(i32 %argc, i8** nocapture %argv) nounwind {
entry:
-; CHECK: test8
+; CHECK-LABEL: test8
; CHECK: strb {{w[0-9]+}}, [sp, #3]
; CHECK: strb wzr, [sp, #2]
; CHECK: strb {{w[0-9]+}}, [sp, #1]
; CHECK: strb wzr, [sp]
; CHECK: bl
-; FAST: test8
+; FAST-LABEL: test8
; FAST: strb {{w[0-9]+}}, [sp]
; FAST: strb {{w[0-9]+}}, [sp, #1]
; FAST: strb {{w[0-9]+}}, [sp, #2]
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll?rev=213703&r1=213702&r2=213703&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll Tue Jul 22 18:14:54 2014
@@ -34,7 +34,7 @@ target triple = "arm64-apple-darwin"
; structs with size < 8 bytes, passed via i64 in x1 and x2
define i32 @f38(i32 %i, i64 %s1.coerce, i64 %s2.coerce) #0 {
entry:
-; CHECK: f38
+; CHECK-LABEL: f38
; CHECK: add w[[A:[0-9]+]], w1, w0
; CHECK: add {{w[0-9]+}}, w[[A]], w2
%s1.sroa.0.0.extract.trunc = trunc i64 %s1.coerce to i32
@@ -56,7 +56,7 @@ entry:
define i32 @caller38() #1 {
entry:
-; CHECK: caller38
+; CHECK-LABEL: caller38
; CHECK: ldr x1,
; CHECK: ldr x2,
%0 = load i64* bitcast (%struct.s38* @g38 to i64*), align 4
@@ -72,7 +72,7 @@ declare i32 @f38_stack(i32 %i, i32 %i2,
; i9 at [sp]
define i32 @caller38_stack() #1 {
entry:
-; CHECK: caller38_stack
+; CHECK-LABEL: caller38_stack
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8]
; CHECK: movz w[[C:[0-9]+]], #0x9
; CHECK: str w[[C]], [sp]
@@ -87,7 +87,7 @@ entry:
; passed via i128 in x1 and x3
define i32 @f39(i32 %i, i128 %s1.coerce, i128 %s2.coerce) #0 {
entry:
-; CHECK: f39
+; CHECK-LABEL: f39
; CHECK: add w[[A:[0-9]+]], w1, w0
; CHECK: add {{w[0-9]+}}, w[[A]], w3
%s1.sroa.0.0.extract.trunc = trunc i128 %s1.coerce to i32
@@ -109,7 +109,7 @@ entry:
define i32 @caller39() #1 {
entry:
-; CHECK: caller39
+; CHECK-LABEL: caller39
; CHECK: ldp x1, x2,
; CHECK: ldp x3, x4,
%0 = load i128* bitcast (%struct.s39* @g39 to i128*), align 16
@@ -125,7 +125,7 @@ declare i32 @f39_stack(i32 %i, i32 %i2,
; passed on stack at [sp+16] and [sp+32]
define i32 @caller39_stack() #1 {
entry:
-; CHECK: caller39_stack
+; CHECK-LABEL: caller39_stack
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32]
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
; CHECK: movz w[[C:[0-9]+]], #0x9
@@ -141,7 +141,7 @@ entry:
; passed via i128 in x1 and x3
define i32 @f40(i32 %i, [2 x i64] %s1.coerce, [2 x i64] %s2.coerce) #0 {
entry:
-; CHECK: f40
+; CHECK-LABEL: f40
; CHECK: add w[[A:[0-9]+]], w1, w0
; CHECK: add {{w[0-9]+}}, w[[A]], w3
%s1.coerce.fca.0.extract = extractvalue [2 x i64] %s1.coerce, 0
@@ -165,7 +165,7 @@ entry:
define i32 @caller40() #1 {
entry:
-; CHECK: caller40
+; CHECK-LABEL: caller40
; CHECK: ldp x1, x2,
; CHECK: ldp x3, x4,
%0 = load [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4
@@ -181,7 +181,7 @@ declare i32 @f40_stack(i32 %i, i32 %i2,
; passed on stack at [sp+8] and [sp+24]
define i32 @caller40_stack() #1 {
entry:
-; CHECK: caller40_stack
+; CHECK-LABEL: caller40_stack
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #24]
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8]
; CHECK: movz w[[C:[0-9]+]], #0x9
@@ -197,7 +197,7 @@ entry:
; passed via i128 in x1 and x3
define i32 @f41(i32 %i, i128 %s1.coerce, i128 %s2.coerce) #0 {
entry:
-; CHECK: f41
+; CHECK-LABEL: f41
; CHECK: add w[[A:[0-9]+]], w1, w0
; CHECK: add {{w[0-9]+}}, w[[A]], w3
%s1.sroa.0.0.extract.trunc = trunc i128 %s1.coerce to i32
@@ -219,7 +219,7 @@ entry:
define i32 @caller41() #1 {
entry:
-; CHECK: caller41
+; CHECK-LABEL: caller41
; CHECK: ldp x1, x2,
; CHECK: ldp x3, x4,
%0 = load i128* bitcast (%struct.s41* @g41 to i128*), align 16
@@ -235,7 +235,7 @@ declare i32 @f41_stack(i32 %i, i32 %i2,
; passed on stack at [sp+16] and [sp+32]
define i32 @caller41_stack() #1 {
entry:
-; CHECK: caller41_stack
+; CHECK-LABEL: caller41_stack
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32]
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
; CHECK: movz w[[C:[0-9]+]], #0x9
@@ -250,7 +250,7 @@ entry:
; structs with size of 22 bytes, passed indirectly in x1 and x2
define i32 @f42(i32 %i, %struct.s42* nocapture %s1, %struct.s42* nocapture %s2) #2 {
entry:
-; CHECK: f42
+; CHECK-LABEL: f42
; CHECK: ldr w[[A:[0-9]+]], [x1]
; CHECK: ldr w[[B:[0-9]+]], [x2]
; CHECK: add w[[C:[0-9]+]], w[[A]], w0
@@ -280,7 +280,7 @@ entry:
; For s1, we allocate a 22-byte space, pass its address via x1
define i32 @caller42() #3 {
entry:
-; CHECK: caller42
+; CHECK-LABEL: caller42
; CHECK: str {{x[0-9]+}}, [sp, #48]
; CHECK: str {{q[0-9]+}}, [sp, #32]
; CHECK: str {{x[0-9]+}}, [sp, #16]
@@ -290,7 +290,7 @@ entry:
; Space for s1 is allocated at sp+32
; Space for s2 is allocated at sp
-; FAST: caller42
+; FAST-LABEL: caller42
; FAST: sub sp, sp, #96
; Space for s1 is allocated at fp-24 = sp+72
; Space for s2 is allocated at sp+48
@@ -316,7 +316,7 @@ declare i32 @f42_stack(i32 %i, i32 %i2,
define i32 @caller42_stack() #3 {
entry:
-; CHECK: caller42_stack
+; CHECK-LABEL: caller42_stack
; CHECK: mov x29, sp
; CHECK: sub sp, sp, #96
; CHECK: stur {{x[0-9]+}}, [x29, #-16]
@@ -333,7 +333,7 @@ entry:
; CHECK: movz w[[C:[0-9]+]], #0x9
; CHECK: str w[[C]], [sp]
-; FAST: caller42_stack
+; FAST-LABEL: caller42_stack
; Space for s1 is allocated at fp-24
; Space for s2 is allocated at fp-48
; FAST: sub x[[A:[0-9]+]], x29, #24
@@ -359,12 +359,12 @@ entry:
; passed indirectly in x1 and x2
define i32 @f43(i32 %i, %struct.s43* nocapture %s1, %struct.s43* nocapture %s2) #2 {
entry:
-; CHECK: f43
+; CHECK-LABEL: f43
; CHECK: ldr w[[A:[0-9]+]], [x1]
; CHECK: ldr w[[B:[0-9]+]], [x2]
; CHECK: add w[[C:[0-9]+]], w[[A]], w0
; CHECK: add {{w[0-9]+}}, w[[C]], w[[B]]
-; FAST: f43
+; FAST-LABEL: f43
; FAST: ldr w[[A:[0-9]+]], [x1]
; FAST: ldr w[[B:[0-9]+]], [x2]
; FAST: add w[[C:[0-9]+]], w[[A]], w0
@@ -388,7 +388,7 @@ entry:
define i32 @caller43() #3 {
entry:
-; CHECK: caller43
+; CHECK-LABEL: caller43
; CHECK: str {{q[0-9]+}}, [sp, #48]
; CHECK: str {{q[0-9]+}}, [sp, #32]
; CHECK: str {{q[0-9]+}}, [sp, #16]
@@ -398,7 +398,7 @@ entry:
; Space for s1 is allocated at sp+32
; Space for s2 is allocated at sp
-; FAST: caller43
+; FAST-LABEL: caller43
; FAST: mov x29, sp
; Space for s1 is allocated at sp+32
; Space for s2 is allocated at sp
@@ -428,7 +428,7 @@ declare i32 @f43_stack(i32 %i, i32 %i2,
define i32 @caller43_stack() #3 {
entry:
-; CHECK: caller43_stack
+; CHECK-LABEL: caller43_stack
; CHECK: mov x29, sp
; CHECK: sub sp, sp, #96
; CHECK: stur {{q[0-9]+}}, [x29, #-16]
@@ -445,7 +445,7 @@ entry:
; CHECK: movz w[[C:[0-9]+]], #0x9
; CHECK: str w[[C]], [sp]
-; FAST: caller43_stack
+; FAST-LABEL: caller43_stack
; FAST: sub sp, sp, #96
; Space for s1 is allocated at fp-32 = sp+64
; Space for s2 is allocated at sp+32
@@ -481,12 +481,12 @@ declare i32 @callee_i128_split(i32 %i, i
define i32 @i128_split() {
entry:
-; CHECK: i128_split
+; CHECK-LABEL: i128_split
; "i128 %0" should be on stack at [sp].
; "i32 8" should be on stack at [sp, #16].
; CHECK: str {{w[0-9]+}}, [sp, #16]
; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp]
-; FAST: i128_split
+; FAST-LABEL: i128_split
; FAST: sub sp, sp, #48
; FAST: mov x[[ADDR:[0-9]+]], sp
; FAST: str {{w[0-9]+}}, [x[[ADDR]], #16]
@@ -504,12 +504,12 @@ declare i32 @callee_i64(i32 %i, i32 %i2,
define i32 @i64_split() {
entry:
-; CHECK: i64_split
+; CHECK-LABEL: i64_split
; "i64 %0" should be in register x7.
; "i32 8" should be on stack at [sp].
; CHECK: ldr x7, [{{x[0-9]+}}]
; CHECK: str {{w[0-9]+}}, [sp]
-; FAST: i64_split
+; FAST-LABEL: i64_split
; FAST: ldr x7, [{{x[0-9]+}}]
; FAST: str {{w[0-9]+}}, [sp]
%0 = load i64* bitcast (%struct.s41* @g41 to i64*), align 16
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