[llvm] r212933 - AArch64: remove unnecessary pseudo-instruction.

[Tim Northover]

Author: tnorthover
Date: Mon Jul 14 06:16:02 2014
New Revision: 212933

URL: http://llvm.org/viewvc/llvm-project?rev=212933&view=rev
Log:
AArch64: remove unnecessary pseudo-instruction.

Sufficiently twisted use of TableGen lets us write patterns directly for f16
(as an i16 promoted to i32) -> f32 conversion.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
    llvm/trunk/test/CodeGen/AArch64/arm64-vcvt_f.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp?rev=212933&r1=212932&r2=212933&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp Mon Jul 14 06:16:02 2014
@@ -634,19 +634,6 @@ bool AArch64ExpandPseudo::expandMI(Machi
     return true;
   }
 
-  case AArch64::FCVTSHpseudo: {
-    MachineOperand Src = MI.getOperand(1);
-    Src.setImplicit();
-    unsigned SrcH =
-        TII->getRegisterInfo().getSubReg(Src.getReg(), AArch64::hsub);
-    auto MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::FCVTSHr))
-                   .addOperand(MI.getOperand(0))
-                   .addReg(SrcH, RegState::Undef)
-                   .addOperand(Src);
-    transferImpOps(MI, MIB, MIB);
-    MI.eraseFromParent();
-    return true;
-  }
   case AArch64::LOADgot: {
     // Expand into ADRP + LDR.
     unsigned DstReg = MI.getOperand(0).getReg();

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=212933&r1=212932&r2=212933&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Mon Jul 14 06:16:02 2014
@@ -2239,8 +2239,9 @@ def : Pat<(f32_to_f16 FPR32:$Rn),
                    (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
                    GPR32))>;
 
-def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
-                          [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
+def : Pat<(f32 (f16_to_f32 i32:$Rn)),
+          (FCVTSHr (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS i32:$Rn, FPR32)),
+                                   hsub))>;
 
 // When converting from f16 coming directly from a load, make sure we
 // load into the FPR16 registers rather than going through the GPRs.

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-vcvt_f.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-vcvt_f.ll?rev=212933&r1=212932&r2=212933&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-vcvt_f.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-vcvt_f.ll Mon Jul 14 06:16:02 2014
@@ -72,8 +72,8 @@ define i16 @to_half(float %in) {
 
 define float @from_half(i16 %in) {
 ; CHECK-LABEL: from_half:
-; CHECK: fmov s[[HALFVAL:[0-9]+]], {{w[0-9]+}}
-; CHECK: fcvt s0, h[[HALFVAL]]
+; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}}
+; CHECK: fcvt s0, {{h[0-9]+}}
   %res = call float @llvm.convert.from.fp16(i16 %in)
   ret float %res
 }