[PATCH] PR18825 - New RegisterCoalescer subtarget hook
cbieneman at apple.com
Fri Jul 11 17:19:54 PDT 2014
I agree completely. I'll look into any codegen differences in our test suite, and in SPEC.
> On Jul 11, 2014, at 4:26 PM, David Peixotto <dpeixott at codeaurora.org> wrote:
> Hi Chris,
> I agree that there is no simple solution. I am not opposed to your heuristic approach. I asked for stats or perf data because I know that the bug rarely happens, but I can't tell from reading the code how often the heuristic will hit. As you mentioned coalescing can have positive or negative performance impact and it would be good to understand if this change has any impact on codegen or performance for some larger benchmarks.
> That's my opinion anyway :)
> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>> -----Original Message-----
>> From: Chris Bieneman [mailto:cbieneman at apple.com]
>> Sent: Friday, July 11, 2014 2:58 PM
>> To: David Peixotto
>> Cc: llvm-commits
>> Subject: Re: [PATCH] PR18825 - New RegisterCoalescer subtarget hook
>> Hi David,
>> I haven’t run SPEC, but I have run all of LLVM’s in tree tests. Among
>> those I haven’t found any codegen differences except the one test that I
>> called out in my original email, and I suspect that would be a performance
>> That said, there are certainly cases where blocking coalescing can
>> generate worse code. I’ve been emailing back and forth with Quentin about
>> potential longer-term solutions to this problem and there really is no
>> simple solution.
>>> On Jul 11, 2014, at 2:45 PM, David Peixotto <dpeixott at codeaurora.org>
>>> Hi Chris,
>>> It would be great to get this bug fixed. I have a general question about
>> the heuristic.
>>> I believe the case we need to avoid in the bug is quite rare (running
>> out of registers), but the heuristic will prevent colaescing in other
>> cases as well. Do you have any statistics for how many coalescings are
>> prevented by the heuristic and any performance data for spec or llvm test
>>> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>>> hosted by The Linux Foundation
>>>> -----Original Message-----
>>>> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
>>>> bounces at cs.uiuc.edu] On Behalf Of Chris Bieneman
>>>> Sent: Friday, July 11, 2014 1:45 PM
>>>> To: llvm-commits
>>>> Subject: [PATCH] PR18825 - New RegisterCoalescer subtarget hook
>>>> The attached patch adds a new subtarget hook to the
>>>> RegisterCoalescer, and an ARM implementation. The ARM implementation
>>>> works around PR18825, and also better code in cases with a large number
>> of NEON vectors in use.
>>>> The basic problem is that the coalescer is very aggressive at
>>>> propagating constraints on the register classes, and the register
>>>> allocator doesn’t know how to split sub-registers later to recover.
>>>> This patch provides an escape valve for targets that encounter this
>> problem to limit coalescing.
>>>> A few other notes about this patch:
>>>> (1) In code that triggers the heuristic (using a lot of large vector
>>>> registers) this code can improve compile time substantially, and in
>>>> other code it has no adverse impact.
>>>> (2) This code also breaks one of the tests in our test suite
>>>> (CodeGen/ARM/vldm-sched-a9.ll). This test is designed to test NEON
>>>> vector spilling, and with this patch the test no longer spills. With
>>>> the final patch I will provide a new test case to test vector
>>>> spilling, and this test will be marked XFAIL so that we don’t regress
>>>> this and start spilling here again.
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