[PATCH 1/2] SelectionDAG: Factor FP_TO_SINT lower code out of DAGLegalizer
Owen Anderson
resistor at mac.com
Thu Jul 10 15:29:45 PDT 2014
LGTM.
—Owen
On Jul 10, 2014, at 8:28 AM, Tom Stellard <tom at stellard.net> wrote:
> Hi Jan,
>
> Both patches, but Owen should look at the LegalizeDAG changes.
>
> -Tom
>
> On Thu, Jul 10, 2014 at 10:28:11AM -0400, Jan Vesely wrote:
>> On Thu, 2014-07-03 at 11:03 -0400, Tom Stellard wrote:
>>> LGTM.
>>
>> Thank you. Is that for both patches or just the first one?
>>
>>>
>>> On Sat, Jun 28, 2014 at 02:22:03PM -0400, Jan Vesely wrote:
>>>> Move the code to a helper function to allow calls from TypeLegalizer.
>>>>
>>>> No functionality change intended
>>>>
>>>> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
>>>> ---
>>>> include/llvm/Target/TargetLowering.h | 6 +++
>>>> lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 61 ++--------------------------
>>>> lib/CodeGen/SelectionDAG/TargetLowering.cpp | 62 +++++++++++++++++++++++++++++
>>>> 3 files changed, 71 insertions(+), 58 deletions(-)
>>>>
>>>> diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
>>>> index 60a4079..dd2bd14 100644
>>>> --- a/include/llvm/Target/TargetLowering.h
>>>> +++ b/include/llvm/Target/TargetLowering.h
>>>> @@ -2530,6 +2530,12 @@ public:
>>>> SDValue LH = SDValue(), SDValue RL = SDValue(),
>>>> SDValue RH = SDValue()) const;
>>>>
>>>> + /// Expand float(f32) to SINT(i64) conversion
>>>> + /// \param N Node to expand
>>>> + /// \param Result output after conversion
>>>> + /// \returns True, if the expansion was successful, false otherwise
>>>> + bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
>>>> +
>>>> //===--------------------------------------------------------------------===//
>>>> // Instruction Emitting Hooks
>>>> //
>>>> diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>>> index eaa51c6..abcfb41 100644
>>>> --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>>> +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>>> @@ -3152,65 +3152,10 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
>>>> Node->getOperand(0), Node->getValueType(0), dl);
>>>> Results.push_back(Tmp1);
>>>> break;
>>>> - case ISD::FP_TO_SINT: {
>>>> - EVT VT = Node->getOperand(0).getValueType();
>>>> - EVT NVT = Node->getValueType(0);
>>>> -
>>>> - // FIXME: Only f32 to i64 conversions are supported.
>>>> - if (VT != MVT::f32 || NVT != MVT::i64)
>>>> - break;
>>>> -
>>>> - // Expand f32 -> i64 conversion
>>>> - // This algorithm comes from compiler-rt's implementation of fixsfdi:
>>>> - // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
>>>> - EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
>>>> - VT.getSizeInBits());
>>>> - SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
>>>> - SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
>>>> - SDValue Bias = DAG.getConstant(127, IntVT);
>>>> - SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
>>>> - IntVT);
>>>> - SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
>>>> - SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
>>>> -
>>>> - SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
>>>> -
>>>> - SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
>>>> - DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
>>>> - DAG.getZExtOrTrunc(ExponentLoBit, dl, TLI.getShiftAmountTy(IntVT)));
>>>> - SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
>>>> -
>>>> - SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
>>>> - DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
>>>> - DAG.getZExtOrTrunc(SignLowBit, dl, TLI.getShiftAmountTy(IntVT)));
>>>> - Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
>>>> -
>>>> - SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
>>>> - DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
>>>> - DAG.getConstant(0x00800000, IntVT));
>>>> -
>>>> - R = DAG.getZExtOrTrunc(R, dl, NVT);
>>>> -
>>>> -
>>>> - R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
>>>> - DAG.getNode(ISD::SHL, dl, NVT, R,
>>>> - DAG.getZExtOrTrunc(
>>>> - DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
>>>> - dl, TLI.getShiftAmountTy(IntVT))),
>>>> - DAG.getNode(ISD::SRL, dl, NVT, R,
>>>> - DAG.getZExtOrTrunc(
>>>> - DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
>>>> - dl, TLI.getShiftAmountTy(IntVT))),
>>>> - ISD::SETGT);
>>>> -
>>>> - SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
>>>> - DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
>>>> - Sign);
>>>> -
>>>> - Results.push_back(DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
>>>> - DAG.getConstant(0, NVT), Ret, ISD::SETLT));
>>>> + case ISD::FP_TO_SINT:
>>>> + if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
>>>> + Results.push_back(Tmp1);
>>>> break;
>>>> - }
>>>> case ISD::FP_TO_UINT: {
>>>> SDValue True, False;
>>>> EVT VT = Node->getOperand(0).getValueType();
>>>> diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>>>> index 75bbbe7..cfb774e 100644
>>>> --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>>>> +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>>>> @@ -2877,3 +2877,65 @@ bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
>>>> }
>>>> return false;
>>>> }
>>>> +
>>>> +bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
>>>> + SelectionDAG &DAG) const {
>>>> + EVT VT = Node->getOperand(0).getValueType();
>>>> + EVT NVT = Node->getValueType(0);
>>>> + SDLoc dl(SDValue(Node, 0));
>>>> +
>>>> + // FIXME: Only f32 to i64 conversions are supported.
>>>> + if (VT != MVT::f32 || NVT != MVT::i64)
>>>> + return false;
>>>> +
>>>> + // Expand f32 -> i64 conversion
>>>> + // This algorithm comes from compiler-rt's implementation of fixsfdi:
>>>> + // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
>>>> + EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
>>>> + VT.getSizeInBits());
>>>> + SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
>>>> + SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
>>>> + SDValue Bias = DAG.getConstant(127, IntVT);
>>>> + SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
>>>> + IntVT);
>>>> + SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
>>>> + SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
>>>> +
>>>> + SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
>>>> +
>>>> + SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
>>>> + DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
>>>> + DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
>>>> + SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
>>>> +
>>>> + SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
>>>> + DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
>>>> + DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
>>>> + Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
>>>> +
>>>> + SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
>>>> + DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
>>>> + DAG.getConstant(0x00800000, IntVT));
>>>> +
>>>> + R = DAG.getZExtOrTrunc(R, dl, NVT);
>>>> +
>>>> +
>>>> + R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
>>>> + DAG.getNode(ISD::SHL, dl, NVT, R,
>>>> + DAG.getZExtOrTrunc(
>>>> + DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
>>>> + dl, getShiftAmountTy(IntVT))),
>>>> + DAG.getNode(ISD::SRL, dl, NVT, R,
>>>> + DAG.getZExtOrTrunc(
>>>> + DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
>>>> + dl, getShiftAmountTy(IntVT))),
>>>> + ISD::SETGT);
>>>> +
>>>> + SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
>>>> + DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
>>>> + Sign);
>>>> +
>>>> + Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
>>>> + DAG.getConstant(0, NVT), Ret, ISD::SETLT);
>>>> + return true;
>>>> +}
>>>> --
>>>> 1.9.3
>>>>
>>>> _______________________________________________
>>>> llvm-commits mailing list
>>>> llvm-commits at cs.uiuc.edu
>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>> --
>> Jan Vesely <jan.vesely at rutgers.edu>
>
>
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