[llvm] r212756 - Extend the test coverage in combine-vec-shuffle-2.ll adding some negative tests.

[Andrea Di Biagio]

Author: adibiagio
Date: Thu Jul 10 13:59:41 2014
New Revision: 212756

URL: http://llvm.org/viewvc/llvm-project?rev=212756&view=rev
Log:
Extend the test coverage in combine-vec-shuffle-2.ll adding some negative tests.

Add test cases where we don't expect to trigger the combine optimizations
introduced at revision 212748.

No functional change intended.



Modified:
    llvm/trunk/test/CodeGen/X86/combine-vec-shuffle-2.ll

Modified: llvm/trunk/test/CodeGen/X86/combine-vec-shuffle-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-vec-shuffle-2.ll?rev=212756&r1=212755&r2=212756&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-vec-shuffle-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-vec-shuffle-2.ll Thu Jul 10 13:59:41 2014
@@ -162,3 +162,92 @@ define <4 x i32> @test14(<4 x i32> %A, <
 ; CHECK-NOT: pshufd
 ; CHECK: ret
 
+
+; Verify that we don't optimize the following cases. We expect more than one shuffle.
+
+define <4 x i32> @test15(<4 x i32> %A, <4 x i32> %B) {
+  %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
+  ret <4 x i32> %2
+}
+; CHECK-LABEL: test15
+; CHECK: shufps $114
+; CHECK-NEXT: pshufd $-58
+; CHECK-NEXT: ret
+
+
+define <4 x i32> @test16(<4 x i32> %A, <4 x i32> %B) {
+  %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
+  ret <4 x i32> %2
+}
+; CHECK-LABEL: test16
+; CHECK: blendps $10
+; CHECK-NEXT: pshufd $-58
+; CHECK-NEXT: ret
+
+
+define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) {
+  %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
+  ret <4 x i32> %2
+}
+; CHECK-LABEL: test17
+; CHECK: shufps $120
+; CHECK-NEXT: pshufd $-58
+; CHECK-NEXT: ret
+
+
+define <4 x i32> @test18(<4 x i32> %A, <4 x i32> %B) {
+  %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
+  ret <4 x i32> %2
+}
+; CHECK-LABEL: test18
+; CHECK: blendps $11
+; CHECK-NEXT: pshufd $-59
+; CHECK-NEXT: ret
+
+define <4 x i32> @test19(<4 x i32> %A, <4 x i32> %B) {
+  %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
+  ret <4 x i32> %2
+}
+; CHECK-LABEL: test19
+; CHECK: shufps $-104
+; CHECK-NEXT: pshufd $2
+; CHECK-NEXT: ret
+
+
+define <4 x i32> @test20(<4 x i32> %A, <4 x i32> %B) {
+  %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
+  ret <4 x i32> %2
+}
+; CHECK-LABEL: test20
+; CHECK: shufps $11
+; CHECK-NEXT: pshufd $-58
+; CHECK-NEXT: ret
+
+
+define <4 x i32> @test21(<4 x i32> %A, <4 x i32> %B) {
+  %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
+  ret <4 x i32> %2
+}
+; CHECK-LABEL: test21
+; CHECK: shufps $120
+; CHECK-NEXT: pshufd $-60
+; CHECK-NEXT: ret
+
+
+define <4 x i32> @test22(<4 x i32> %A, <4 x i32> %B) {
+  %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
+  ret <4 x i32> %2
+}
+; CHECK-LABEL: test22
+; CHECK: blendps $11
+; CHECK-NEXT: pshufd $-43
+; CHECK-NEXT: ret
+