[PATCH] [x86] Add a ZERO_EXTEND_VECTOR_INREG DAG node and use it when widening vector types to be legal and a ZERO_EXTEND node is encountered.
nrotem at apple.com
Mon Jul 7 16:50:02 PDT 2014
> On Jul 7, 2014, at 3:20 AM, Chandler Carruth <chandlerc at gmail.com> wrote:
> Hi grosbach, filcab, hfinkel, echristo, bkramer,
> When we use widening to legalize vector types, extend nodes are a real
> challenge. Either the input or output is likely to be legal, but in many
> cases not both. As a consequence, we don't really have any way to
> represent this situation and the prior code in the widening legalization
> framework would just scalarize the extend operation completely.
> This patch introduces a new DAG node to represent doing a zero extend of
> a vector "in register". The core of the idea is to allow legal but
> different vector types in the input and output. The output vector must
> have fewer lanes but wider elements. The operation is defined to zero
> extend the low elements of the input to the size of the output elements,
> and drop all of the high elements which don't have a corresponding lane
> in the output vector.
> It also includes generic expansion of this node in terms of blending
> a zero vector into the high elements of the vector and bitcasting
> across. This in turn yields extremely nice code for x86 SSE2 when we use
> the new widening legalization logic in conjunction with the new shuffle
> lowering logic.
> There is still more to do here. We need to support sign extension, any
> extension, and potentially int-to-float conversions. My current plan is
> to continue using similar synthetic nodes to model each of these
> transitions with generic lowering code for each one.
> However, with this patch LLVM already reaches performance parity with
> GCC for the core C loops of the x264 code (assuming you disable the
> hand-written assembly versions) when compiling for SSE2 and SSE3
> architectures and enabling the new widening and lowering logic for
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