[PATCH] [AArch64] Enhance rematerialization by adding a new API isAsCheapAsAMove in TargetInstroInfo

[Jiangning Liu]

Hi Quentin,

The issues you mentioned are all fixed except adding isAsCheapAsMove flag in .td file.

Thanks,
-Jiangning

================
Comment at: include/llvm/Target/TargetInstrInfo.h:206
@@ +205,3 @@
+  ///
+  /// Targets for different archs need to override this, and different u-archs
+  /// can also be finely tuned inside.
----------------
Quentin Colombet wrote:
> Like Eric said:
> u-archs => microarchitectures
Fixed in new version.

================
Comment at: lib/Target/AArch64/AArch64InstrFormats.td:1681
@@ -1680,3 +1680,3 @@
 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> {
-  let isCompare = 1, Defs = [NZCV] in {
+  let isCompare = 1, Defs = [NZCV], isReMaterializable = 1 in {
   // Add/Subtract immediate
----------------
Quentin Colombet wrote:
> I believe this is a remaining of the rematerialization of the  S variants. This should be removed. 
Removed in new version.

================
Comment at: lib/Target/AArch64/AArch64InstrFormats.td:1954
@@ -1953,3 +1953,3 @@
 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode> {
-  let isCompare = 1, Defs = [NZCV] in {
+  let isCompare = 1, Defs = [NZCV], isReMaterializable = 1 in {
   def Wri  : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
----------------
Quentin Colombet wrote:
> Same here: Shouldn't be rematerializable.
Removed in new version.

================
Comment at: lib/Target/AArch64/AArch64InstrFormats.td:2001
@@ -1999,1 +2000,3 @@
+  let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0,
+      isReMaterializable = 1 in {
   def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
----------------
Quentin Colombet wrote:
> Ditto.
Removed in new version.

http://reviews.llvm.org/D4361