[PATCH] [x86] Begin a significant overhaul of how vector lowering is done in the x86 backend.

[Filipe Cabecinhas]

LGTM, too. I'll still have another look at some comments, but if there's any minor issue with those, it can be resolved on IRC.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:6782
@@ +6781,3 @@
+// NB: We rely heavily on "undef" masks preserving the input lane.
+static SDValue getV4ShuffleImmForMask(ArrayRef<int> Mask, SelectionDAG &DAG) {
+  assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
----------------
Chandler Carruth wrote:
> Filipe Cabecinhas wrote:
> > This is similar to a (DAG) shuffle mask, but not quite (it only goes up (non-inclusive) to 4, not 8, which you would have on shuffles for two v4* vectors). Could you add some word (Shufp?) to the name, to make it easier to spot the difference?
> Do you have a concrete suggestion here? I don't have any ideas other than V4. We use this for SHUFP, PSHUF, PSHUFH, and PSHUFL instructions. =/
> 
> The way I think about it is that this is just the way that x86 always represents a 4-lane shuffle, regardless of where the 4 lanes come from.
Maybe V4X86Shuffle? At least it shows it might not be a “regular” DAG shuffle mask.

http://reviews.llvm.org/D4225