[llvm] r211694 - [x86] Add intrinsics for the pshufd, pshuflw, and pshufhw instructions.

[Hal Finkel]

----- Original Message -----
> From: "Chandler Carruth" <chandlerc at gmail.com>
> To: "Craig Topper" <craig.topper at gmail.com>
> Cc: llvm-commits at cs.uiuc.edu
> Sent: Wednesday, June 25, 2014 10:54:20 AM
> Subject: Re: [llvm] r211694 - [x86] Add intrinsics for the pshufd, pshuflw,	and pshufhw instructions.
> 
> 
> 
> 
> 
> On Wed, Jun 25, 2014 at 5:18 PM, Craig Topper <
> craig.topper at gmail.com > wrote:
> 
> 
> 
> What's the motivation? Can't these be represented with appropriate
> shufflevector indices?
> 
> 
> My motivation is testing, nothing more.
> 
> 
> They can certainly be represented with appropriate shufflevector
> instructions, but then those go through the entire generic combiner
> and lowering which makes testing the target-specific combines quite
> a bit harder (the independent ones almost always nuke them).

I don't understand this; what do you mean? Exactly what are you testing?

 -Hal

> 
> 
> It also seems nice to support them as GCC documents the builtins and
> this get's us those builtins for "free".
> 
> 
> 
> 
> 
> 
> 
> 
> On Wed, Jun 25, 2014 at 6:12 AM, Chandler Carruth <
> chandlerc at gmail.com > wrote:
> 
> 
> Author: chandlerc
> Date: Wed Jun 25 08:12:54 2014
> New Revision: 211694
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=211694&view=rev
> Log:
> [x86] Add intrinsics for the pshufd, pshuflw, and pshufhw
> instructions.
> 
> Modified:
> llvm/trunk/include/llvm/IR/IntrinsicsX86.td
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll
> 
> Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=211694&r1=211693&r2=211694&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)
> +++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Wed Jun 25 08:12:54
> 2014
> @@ -667,6 +667,15 @@ let TargetPrefix = "x86" in { // All in
> def int_x86_ssse3_pshuf_b_128 :
> GCCBuiltin<"__builtin_ia32_pshufb128">,
> Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty,
> llvm_v16i8_ty], [IntrNoMem]>;
> + def int_x86_sse2_pshuf_d : GCCBuiltin<"__builtin_ia32_pshufd">,
> + Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i8_ty],
> + [IntrNoMem]>;
> + def int_x86_sse2_pshufl_w : GCCBuiltin<"__builtin_ia32_pshuflw">,
> + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i8_ty],
> + [IntrNoMem]>;
> + def int_x86_sse2_pshufh_w : GCCBuiltin<"__builtin_ia32_pshufhw">,
> + Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i8_ty],
> + [IntrNoMem]>;
> def int_x86_sse_pshuf_w : GCCBuiltin<"__builtin_ia32_pshufw">,
> Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_i8_ty],
> [IntrNoMem]>;
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=211694&r1=211693&r2=211694&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jun 25 08:12:54
> 2014
> @@ -12660,6 +12660,18 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
> return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
> Op.getOperand(1), Op.getOperand(2));
> 
> + case Intrinsic::x86_sse2_pshuf_d:
> + return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
> + Op.getOperand(1), Op.getOperand(2));
> +
> + case Intrinsic::x86_sse2_pshufl_w:
> + return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
> + Op.getOperand(1), Op.getOperand(2));
> +
> + case Intrinsic::x86_sse2_pshufh_w:
> + return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
> + Op.getOperand(1), Op.getOperand(2));
> +
> case Intrinsic::x86_ssse3_psign_b_128:
> case Intrinsic::x86_ssse3_psign_w_128:
> case Intrinsic::x86_ssse3_psign_d_128:
> 
> Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=211694&r1=211693&r2=211694&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll Wed Jun 25
> 08:12:54 2014
> @@ -717,3 +717,30 @@ define void @test_x86_sse2_pause() {
> ret void
> }
> declare void @llvm.x86.sse2.pause() nounwind
> +
> +define <4 x i32> @test_x86_sse2_pshuf_d(<4 x i32> %a) {
> +; CHECK-LABEL: test_x86_sse2_pshuf_d:
> +; CHECK: pshufd $27
> +entry:
> + %res = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
> nounwind readnone
> + ret <4 x i32> %res
> +}
> +declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8) nounwind
> readnone
> +
> +define <8 x i16> @test_x86_sse2_pshufl_w(<8 x i16> %a) {
> +; CHECK-LABEL: test_x86_sse2_pshufl_w:
> +; CHECK: pshuflw $27
> +entry:
> + %res = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
> nounwind readnone
> + ret <8 x i16> %res
> +}
> +declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8) nounwind
> readnone
> +
> +define <8 x i16> @test_x86_sse2_pshufh_w(<8 x i16> %a) {
> +; CHECK-LABEL: test_x86_sse2_pshufh_w:
> +; CHECK: pshufhw $27
> +entry:
> + %res = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
> nounwind readnone
> + ret <8 x i16> %res
> +}
> +declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8) nounwind
> readnone
> 
> 
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> 
> --
> ~Craig
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-- 
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory