[PATCH 1/1] R600: Implement float to long/ulong
Matt Arsenault
Matthew.Arsenault at amd.com
Tue Jun 24 13:34:46 PDT 2014
On 06/24/2014 01:29 PM, Jan Vesely wrote:
> Use alg. from LegalizeDAG.cpp
> Move Expand setting to SIISellowering
>
> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
> ---
>
> Behavior for out of bounds conversions is implementation defined, so I did not
> bother checking. It also makes the signed version work OK for ulong.
>
> lib/Target/R600/AMDGPUISelLowering.cpp | 1 -
> lib/Target/R600/R600ISelLowering.cpp | 62 +++++-
> lib/Target/R600/SIISelLowering.cpp | 3 +
> test/CodeGen/R600/conv.ll | 350 +++++++++++++++++++++++++++++++++
> 4 files changed, 414 insertions(+), 2 deletions(-)
> create mode 100644 test/CodeGen/R600/conv.ll
These tests should go in the already existing
fp_to_sint.ll/fp_to_uint.ll tests. There is actually a fp_to_sint_i64.ll
with a FIXME to move it when it's fixed for evergreen
>
> diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
> index 07c82b1..500b0e5 100644
> --- a/lib/Target/R600/AMDGPUISelLowering.cpp
> +++ b/lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -265,7 +265,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
> setOperationAction(ISD::ROTL, MVT::i64, Expand);
> setOperationAction(ISD::ROTR, MVT::i64, Expand);
>
> - setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
> setOperationAction(ISD::MUL, MVT::i64, Expand);
> setOperationAction(ISD::MULHU, MVT::i64, Expand);
> setOperationAction(ISD::MULHS, MVT::i64, Expand);
> diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
> index 13d555e..f021399 100644
> --- a/lib/Target/R600/R600ISelLowering.cpp
> +++ b/lib/Target/R600/R600ISelLowering.cpp
> @@ -82,6 +82,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
> setOperationAction(ISD::SETCC, MVT::i32, Expand);
> setOperationAction(ISD::SETCC, MVT::f32, Expand);
> setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
> + setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
> + setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
>
> setOperationAction(ISD::SELECT, MVT::i32, Expand);
> setOperationAction(ISD::SELECT, MVT::f32, Expand);
> @@ -829,8 +831,66 @@ void R600TargetLowering::ReplaceNodeResults(SDNode *N,
> default:
> AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
> return;
> - case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
> + case ISD::FP_TO_UINT:
> + if (N->getValueType(0) == MVT::i1) {
> + Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
> + return;
> + }
> + case ISD::FP_TO_SINT: {
> + // Expand f32 -> i64 conversion
> + // This algorithm comes from compiler-rt's implementation of fixsfdi:
> + // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
> + EVT VT = N->getOperand(0).getValueType();
> + EVT NVT = N->getValueType(0);
> + SDValue Op = SDValue(N, 0);
> + SDLoc DL(Op);
> + EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
> + SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
> + SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
> + SDValue Bias = DAG.getConstant(127, IntVT);
> + SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
> + IntVT);
> + SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
> + SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
> +
> + SDValue Bits = DAG.getNode(ISD::BITCAST, DL, IntVT, N->getOperand(0));
> +
> + SDValue ExponentBits = DAG.getNode(ISD::SRL, DL, IntVT,
> + DAG.getNode(ISD::AND, DL, IntVT, Bits, ExponentMask),
> + DAG.getZExtOrTrunc(ExponentLoBit, DL, getShiftAmountTy(IntVT)));
> + SDValue Exponent = DAG.getNode(ISD::SUB, DL, IntVT, ExponentBits, Bias);
> +
> + SDValue Sign = DAG.getNode(ISD::SRA, DL, IntVT,
> + DAG.getNode(ISD::AND, DL, IntVT, Bits, SignMask),
> + DAG.getZExtOrTrunc(SignLowBit, DL, getShiftAmountTy(IntVT)));
> + Sign = DAG.getSExtOrTrunc(Sign, DL, NVT);
> +
> + SDValue R = DAG.getNode(ISD::OR, DL, IntVT,
> + DAG.getNode(ISD::AND, DL, IntVT, Bits, MantissaMask),
> + DAG.getConstant(0x00800000, IntVT));
> +
> + R = DAG.getZExtOrTrunc(R, DL, NVT);
> +
> +
> + R = DAG.getSelectCC(DL, Exponent, ExponentLoBit,
> + DAG.getNode(ISD::SHL, DL, NVT, R,
> + DAG.getZExtOrTrunc(
> + DAG.getNode(ISD::SUB, DL, IntVT, Exponent, ExponentLoBit),
> + DL, getShiftAmountTy(IntVT))),
> + DAG.getNode(ISD::SRL, DL, NVT, R,
> + DAG.getZExtOrTrunc(
> + DAG.getNode(ISD::SUB, DL, IntVT, ExponentLoBit, Exponent),
> + DL, getShiftAmountTy(IntVT))),
> + ISD::SETGT);
> +
> + SDValue Ret = DAG.getNode(ISD::SUB, DL, NVT,
> + DAG.getNode(ISD::XOR, DL, NVT, R, Sign),
> + Sign);
> +
> + Results.push_back(DAG.getSelectCC(DL, Exponent, DAG.getConstant(0, IntVT),
> + DAG.getConstant(0, NVT), Ret, ISD::SETLT));
> return;
> + }
> case ISD::LOAD: {
> SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
> Results.push_back(SDValue(Node, 0));
> diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
> index 4a7e99a..0f66f45 100644
> --- a/lib/Target/R600/SIISelLowering.cpp
> +++ b/lib/Target/R600/SIISelLowering.cpp
> @@ -167,6 +167,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
>
> setOperationAction(ISD::LOAD, MVT::i1, Custom);
>
> + setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
> + setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
> +
> setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
> setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
> setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
> diff --git a/test/CodeGen/R600/conv.ll b/test/CodeGen/R600/conv.ll
> new file mode 100644
> index 0000000..adea0da
> --- /dev/null
> +++ b/test/CodeGen/R600/conv.ll
> @@ -0,0 +1,350 @@
> +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s
> +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
> +
> +; FUNC: @test_long
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +
> +; SI: S_ENDPGM
> +define void @test_long(i64 addrspace(1)* %out, float %x) {
> + %conv = fptosi float %x to i64
> + store i64 %conv, i64 addrspace(1)* %out
> + ret void
> +}
> +
> +; FUNC: @test_ulong
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +
> +; SI: S_ENDPGM
> +define void @test_ulong(i64 addrspace(1)* %out, float %x) {
> + %conv = fptoui float %x to i64
> + store i64 %conv, i64 addrspace(1)* %out
> + ret void
> +}
> +
> +; FUNC: @test_long_v2
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +
> +; SI: S_ENDPGM
> +define void @test_long_v2(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
> + %conv = fptosi <2 x float> %x to <2 x i64>
> + store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
> + ret void
> +}
> +
> +; FUNC: @test_ulong_v2
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +
> +; SI: S_ENDPGM
> +define void @test_ulong_v2(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
> + %conv = fptoui <2 x float> %x to <2 x i64>
> + store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
> + ret void
> +}
> +
> +; FUNC: @test_long_v4
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +
> +; SI: S_ENDPGM
> +define void @test_long_v4(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
> + %conv = fptosi <4 x float> %x to <4 x i64>
> + store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
> + ret void
> +}
> +
> +; FUNC: @test_ulong_v4
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: LSHR
> +; EG-DAG: SUB_INT
> +; EG-DAG: AND_INT
> +; EG-DAG: ASHR
> +; EG-DAG: AND_INT
> +; EG-DAG: OR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHL
> +; EG-DAG: LSHL
> +; EG-DAG: SUB_INT
> +; EG-DAG: LSHR
> +; EG-DAG: LSHR
> +; EG-DAG: SETGT_UINT
> +; EG-DAG: SETGT_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: XOR_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: CNDGE_INT
> +; EG-DAG: CNDGE_INT
> +
> +; SI: S_ENDPGM
> +define void @test_ulong_v4(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
> + %conv = fptoui <4 x float> %x to <4 x i64>
> + store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
> + ret void
> +}
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