[llvm] r211590 - [mips] Added support for assembling sdbbp.
Daniel Sanders
daniel.sanders at imgtec.com
Tue Jun 24 06:00:32 PDT 2014
Author: dsanders
Date: Tue Jun 24 08:00:32 2014
New Revision: 211590
URL: http://llvm.org/viewvc/llvm-project?rev=211590&view=rev
Log:
[mips] Added support for assembling sdbbp.
Summary:
This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the
restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too.
Differential Revision: http://reviews.llvm.org/D4265
Modified:
llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/mips32/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td?rev=211590&r1=211589&r2=211590&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td Tue Jun 24 08:00:32 2014
@@ -97,6 +97,7 @@ def OPCODE6_DCLO : OPCODE6<0b010011>
def OPCODE6_DCLZ : OPCODE6<0b010010>;
def OPCODE6_LSA : OPCODE6<0b000101>;
def OPCODE6_DLSA : OPCODE6<0b010101>;
+def OPCODE6_SDBBP : OPCODE6<0b001110>;
class FIELD_FMT<bits<5> Val> {
bits<5> Value = Val;
@@ -328,6 +329,16 @@ class SPECIAL_3R_FM<bits<5> mulop, bits<
let Inst{5-0} = funct;
}
+class SPECIAL_SDBBP_FM : MipsR6Inst {
+ bits<20> code_;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = OPGROUP_SPECIAL.Value;
+ let Inst{25-6} = code_;
+ let Inst{5-0} = OPCODE6_SDBBP.Value;
+}
+
// This class is ambiguous with other branches:
// BEQC/BNEC require that rs > rt
class CMP_BRANCH_2R_OFF16_FM<OPGROUP funct> : MipsR6Inst {
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=211590&r1=211589&r2=211590&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Tue Jun 24 08:00:32 2014
@@ -16,7 +16,6 @@ include "Mips32r6InstrFormats.td"
// Notes about removals/changes from MIPS32r6:
// Reencoded: jr -> jalr
// Reencoded: jr.hb -> jalr.hb
-// Reencoded: sdbbp
def brtarget21 : Operand<OtherVT> {
let EncoderMethod = "getBranchTarget21OpValue";
@@ -168,6 +167,14 @@ class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCO
class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;
class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;
+class SDBBP_R6_ENC : SPECIAL_SDBBP_FM;
+
+//===----------------------------------------------------------------------===//
+//
+// Instruction Multiclasses
+//
+//===----------------------------------------------------------------------===//
+
class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
RegisterOperand FGROpnd,
SDPatternOperator Op = null_frag> {
@@ -177,12 +184,6 @@ class CMP_CONDN_DESC_BASE<string CondStr
list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
}
-//===----------------------------------------------------------------------===//
-//
-// Instruction Multiclasses
-//
-//===----------------------------------------------------------------------===//
-
multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
RegisterOperand FGROpnd>{
def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
@@ -626,6 +627,13 @@ class CLZ_R6_DESC_BASE<string instr_asm,
class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>;
class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>;
+class SDBBP_R6_DESC {
+ dag OutOperandList = (outs);
+ dag InOperandList = (ins uimm20:$code_);
+ string AsmString = "sdbbp\t$code_";
+ list<dag> Pattern = [];
+}
+
//===----------------------------------------------------------------------===//
//
// Instruction Definitions
@@ -706,6 +714,7 @@ def PREF_R6 : PREF_ENC, PREF_DESC, ISA_M
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
+def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
@@ -719,6 +728,14 @@ def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC,
//===----------------------------------------------------------------------===//
//
+// Instruction Aliases
+//
+//===----------------------------------------------------------------------===//
+
+def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
+
+//===----------------------------------------------------------------------===//
+//
// Patterns and Pseudo Instructions
//
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=211590&r1=211589&r2=211590&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Tue Jun 24 08:00:32 2014
@@ -844,6 +844,16 @@ class BARRIER_FM<bits<5> op> : StdArch {
let Inst{5-0} = 0; // SLL
}
+class SDBBP_FM : StdArch {
+ bits<20> code_;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0b011100; // SPECIAL2
+ let Inst{25-6} = code_;
+ let Inst{5-0} = 0b111111; // SDBBP
+}
+
class JR_HB_FM<bits<6> op> : StdArch{
bits<5> rs;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=211590&r1=211589&r2=211590&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Jun 24 08:00:32 2014
@@ -1180,6 +1180,7 @@ def TNEI : MMRel, TEQI_FT<"tnei", GPR32O
def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
def TRAP : TrapBase<BREAK>;
+def SDBBP : SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
@@ -1488,6 +1489,7 @@ def : MipsInstAlias<"sra $rd, $rt, $rs",
(SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"srl $rd, $rt, $rs",
(SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
def : MipsInstAlias<"sync",
(SYNC 0), 1>, ISA_MIPS2;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/Mips/mips32/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32/valid.s?rev=211590&r1=211589&r2=211590&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32/valid.s Tue Jun 24 08:00:32 2014
@@ -115,6 +115,8 @@
round.w.s $f27,$f28
sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
+ sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
+ sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sh $14,-6704($15)
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=211590&r1=211589&r2=211590&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Tue Jun 24 08:00:32 2014
@@ -140,6 +140,8 @@
round.w.s $f27,$f28
sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
+ sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
+ sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14)
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=211590&r1=211589&r2=211590&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Tue Jun 24 08:00:32 2014
@@ -148,5 +148,7 @@
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
+ sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
+ sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=211590&r1=211589&r2=211590&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Tue Jun 24 08:00:32 2014
@@ -176,6 +176,8 @@
sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
+ sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
+ sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sd $12,5835($10)
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=211590&r1=211589&r2=211590&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Tue Jun 24 08:00:32 2014
@@ -201,6 +201,8 @@
sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
+ sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
+ sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
sd $12,5835($10)
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=211590&r1=211589&r2=211590&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Tue Jun 24 08:00:32 2014
@@ -167,5 +167,7 @@
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
+ sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
+ sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
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