[PATCH 2/3] R600: Implement 64bit SRL
Jan Vesely
jan.vesely at rutgers.edu
Wed Jun 18 05:40:33 PDT 2014
On Tue, 2014-06-17 at 14:20 -0700, Tom Stellard wrote:
> On Tue, Jun 17, 2014 at 04:50:04PM -0400, Jan Vesely wrote:
> > Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
> > ---
> > lib/Target/R600/R600ISelLowering.cpp | 41 ++++++++++++
> > lib/Target/R600/R600ISelLowering.h | 1 +
> > test/CodeGen/R600/srl.ll | 126 +++++++++++++++++++++++++++++++++++
> > 3 files changed, 168 insertions(+)
> >
> > diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
> > index 33dc1b3..e314aca 100644
> > --- a/lib/Target/R600/R600ISelLowering.cpp
> > +++ b/lib/Target/R600/R600ISelLowering.cpp
> > @@ -160,6 +160,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
> > // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
> > // to be Legal/Custom in order to avoid library calls.
> > setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
> > + setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
> >
> > setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
> >
> > @@ -557,6 +558,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
> > case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
> > case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
> > case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
> > + case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
> > case ISD::FCOS:
> > case ISD::FSIN: return LowerTrig(Op, DAG);
> > case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
> > @@ -947,6 +949,45 @@ SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
> > return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
> > }
> >
> > +SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
> > + SDLoc DL(Op);
> > + EVT VT = Op.getValueType();
> > +
> > + SDValue Lo = Op.getOperand(0);
> > + SDValue Hi = Op.getOperand(1);
> > + SDValue Shift = Op.getOperand(2);
> > + SDValue Zero = DAG.getConstant(0, VT);
> > + SDValue One = DAG.getConstant(1, VT);
> > +
> > + SDValue Width = DAG.getConstant(VT.getSizeInBits(), VT);
> > + SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, VT);
> > + SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
> > + SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
> > +
> > + /* The dance around Width1 is necessary for 0 special case.
> > + * Without it the CompShift might be 32, producing incorrect results in
> > + * Overflow. So we do the shift in two steps, the alternative is to
> > + * add a conditional to filter the special case.
> > + */
>
> c++ style comments here, otherwise LGTM.
thanks, I made the changes and pushed all three.
>
> > +
> > + SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
> > + Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
> > +
> > + // TODO: SRA support here
> > + SDValue HiSmall = DAG.getNode(ISD::SRL, DL, VT, Hi, Shift);
> > + SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
> > + LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
> > +
> > + // TODO: SRA support here
> > + SDValue LoBig = DAG.getNode(ISD::SRL, DL, VT, Hi, BigShift);
> > + SDValue HiBig = Zero;
> > +
> > + Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
> > + Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
> > +
> > + return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
> > +}
> > +
> > SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
> > return DAG.getNode(
> > ISD::SETCC,
> > diff --git a/lib/Target/R600/R600ISelLowering.h b/lib/Target/R600/R600ISelLowering.h
> > index a7d8374..381642a 100644
> > --- a/lib/Target/R600/R600ISelLowering.h
> > +++ b/lib/Target/R600/R600ISelLowering.h
> > @@ -61,6 +61,7 @@ private:
> > SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
> > SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
> > SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
> > + SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const;
> >
> > SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
> > SelectionDAG &DAG) const;
> > diff --git a/test/CodeGen/R600/srl.ll b/test/CodeGen/R600/srl.ll
> > index 7637355..44ad73f 100644
> > --- a/test/CodeGen/R600/srl.ll
> > +++ b/test/CodeGen/R600/srl.ll
> > @@ -39,3 +39,129 @@ define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %i
> > store <4 x i32> %result, <4 x i32> addrspace(1)* %out
> > ret void
> > }
> > +
> > +;EG-CHECK: @lshr_i64
> > +;EG-CHECK: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
> > +;EG-CHECK: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
> > +;EG-CHECK: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
> > +;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
> > +;EG-CHECK-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
> > +;EG-CHECK-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
> > +;EG-CHECK-DAG: LSHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
> > +;EG-CHECK-DAG: LSHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
> > +;EG-CHECK-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
> > +;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
> > +;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0
> > +
> > +;SI-CHECK: @lshr_i64
> > +;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> > +
> > +define void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
> > + %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1
> > + %a = load i64 addrspace(1) * %in
> > + %b = load i64 addrspace(1) * %b_ptr
> > + %result = lshr i64 %a, %b
> > + store i64 %result, i64 addrspace(1)* %out
> > + ret void
> > +}
> > +
> > +;EG-CHECK: @lshr_v2i64
> > +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
> > +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
> > +;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]]
> > +;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]]
> > +;EG-CHECK-DAG: LSHL {{.*}}, 1
> > +;EG-CHECK-DAG: LSHL {{.*}}, 1
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
> > +;EG-CHECK-DAG: OR_INT
> > +;EG-CHECK-DAG: OR_INT
> > +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
> > +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
> > +;EG-CHECK-DAG: LSHR
> > +;EG-CHECK-DAG: LSHR
> > +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
> > +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
> > +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> > +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> > +;EG-CHECK-DAG: CNDE_INT
> > +;EG-CHECK-DAG: CNDE_INT
> > +
> > +;SI-CHECK: @lshr_v2i64
> > +;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> > +;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> > +
> > +define void @lshr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
> > + %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1
> > + %a = load <2 x i64> addrspace(1) * %in
> > + %b = load <2 x i64> addrspace(1) * %b_ptr
> > + %result = lshr <2 x i64> %a, %b
> > + store <2 x i64> %result, <2 x i64> addrspace(1)* %out
> > + ret void
> > +}
> > +
> > +
> > +;EG-CHECK: @lshr_v4i64
> > +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
> > +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
> > +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
> > +;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
> > +;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]]
> > +;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]]
> > +;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHC]]
> > +;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHD]]
> > +;EG-CHECK-DAG: LSHL {{.*}}, 1
> > +;EG-CHECK-DAG: LSHL {{.*}}, 1
> > +;EG-CHECK-DAG: LSHL {{.*}}, 1
> > +;EG-CHECK-DAG: LSHL {{.*}}, 1
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHC]]
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHD]]
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHC]]
> > +;EG-CHECK-DAG: LSHR {{.*}}, [[SHD]]
> > +;EG-CHECK-DAG: OR_INT
> > +;EG-CHECK-DAG: OR_INT
> > +;EG-CHECK-DAG: OR_INT
> > +;EG-CHECK-DAG: OR_INT
> > +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
> > +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
> > +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
> > +;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
> > +;EG-CHECK-DAG: LSHR
> > +;EG-CHECK-DAG: LSHR
> > +;EG-CHECK-DAG: LSHR
> > +;EG-CHECK-DAG: LSHR
> > +;EG-CHECK-DAG: LSHR
> > +;EG-CHECK-DAG: LSHR
> > +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
> > +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
> > +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
> > +;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
> > +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> > +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> > +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> > +;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
> > +;EG-CHECK-DAG: CNDE_INT
> > +;EG-CHECK-DAG: CNDE_INT
> > +;EG-CHECK-DAG: CNDE_INT
> > +;EG-CHECK-DAG: CNDE_INT
> > +
> > +;SI-CHECK: @lshr_v4i64
> > +;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> > +;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> > +;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> > +;SI-CHECK: V_LSHR_B64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
> > +
> > +define void @lshr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
> > + %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1
> > + %a = load <4 x i64> addrspace(1) * %in
> > + %b = load <4 x i64> addrspace(1) * %b_ptr
> > + %result = lshr <4 x i64> %a, %b
> > + store <4 x i64> %result, <4 x i64> addrspace(1)* %out
> > + ret void
> > +}
> > --
> > 1.9.3
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
--
Jan Vesely <jan.vesely at rutgers.edu>
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