[llvm] r210908 - [mips][mips64r6] Relocation R_MIPS_PC18_S3
Zoran Jovanovic
zoran.jovanovic at imgtec.com
Fri Jun 13 07:26:47 PDT 2014
Author: zjovanovic
Date: Fri Jun 13 09:26:47 2014
New Revision: 210908
URL: http://llvm.org/viewvc/llvm-project?rev=210908&view=rev
Log:
[mips][mips64r6] Relocation R_MIPS_PC18_S3
Differential Revision: http://reviews.llvm.org/D3890
Modified:
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/mips64r6/relocations.s
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=210908&r1=210907&r2=210908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Fri Jun 13 09:26:47 2014
@@ -111,6 +111,13 @@ static unsigned adjustFixupValue(const M
if (!isIntN(16, Value) && Ctx)
Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
break;
+ case Mips::fixup_MIPS_PC18_S3:
+ // Forcing a signed division because Value can be negative.
+ Value = (int64_t)Value / 8;
+ // We now check if Value can be encoded as a 18-bit signed immediate.
+ if (!isIntN(18, Value) && Ctx)
+ Ctx->FatalError(Fixup.getLoc(), "out of range PC18 fixup");
+ break;
case Mips::fixup_MIPS_PC21_S2:
Value -= 4;
// Forcing a signed division because Value can be negative.
@@ -254,6 +261,7 @@ getFixupKindInfo(MCFixupKind Kind) const
{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
+ { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
@@ -316,6 +324,7 @@ getFixupKindInfo(MCFixupKind Kind) const
{ "fixup_Mips_GOT_LO16", 16, 16, 0 },
{ "fixup_Mips_CALL_HI16", 16, 16, 0 },
{ "fixup_Mips_CALL_LO16", 16, 16, 0 },
+ { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp?rev=210908&r1=210907&r2=210908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Fri Jun 13 09:26:47 2014
@@ -196,6 +196,9 @@ unsigned MipsELFObjectWriter::GetRelocTy
case Mips::fixup_MIPS_PC19_S2:
Type = ELF::R_MIPS_PC19_S2;
break;
+ case Mips::fixup_MIPS_PC18_S3:
+ Type = ELF::R_MIPS_PC18_S3;
+ break;
case Mips::fixup_MIPS_PC21_S2:
Type = ELF::R_MIPS_PC21_S2;
break;
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h?rev=210908&r1=210907&r2=210908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h Fri Jun 13 09:26:47 2014
@@ -128,6 +128,9 @@ namespace Mips {
// resulting in - R_MIPS_CALL_LO16
fixup_Mips_CALL_LO16,
+ // resulting in - R_MIPS_PC18_S3
+ fixup_MIPS_PC18_S3,
+
// resulting in - R_MIPS_PC19_S2
fixup_MIPS_PC19_S2,
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=210908&r1=210907&r2=210908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Fri Jun 13 09:26:47 2014
@@ -642,11 +642,21 @@ unsigned
MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
- assert(MI.getOperand(OpNo).isImm());
- // The immediate is encoded as 'immediate << 3'.
- unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
- assert((Res & 7) == 0);
- return Res >> 3;
+ const MCOperand &MO = MI.getOperand(OpNo);
+ if (MO.isImm()) {
+ // The immediate is encoded as 'immediate << 3'.
+ unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
+ assert((Res & 7) == 0);
+ return Res >> 3;
+ }
+
+ assert(MO.isExpr() &&
+ "getSimm18Lsl2Encoding expects only expressions or an immediate");
+
+ const MCExpr *Expr = MO.getExpr();
+ Fixups.push_back(MCFixup::Create(0, Expr,
+ MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
+ return 0;
}
#include "MipsGenMCCodeEmitter.inc"
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=210908&r1=210907&r2=210908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Jun 13 09:26:47 2014
@@ -365,6 +365,7 @@ def simm19_lsl2 : Operand<i32> {
def simm18_lsl3 : Operand<i32> {
let EncoderMethod = "getSimm18Lsl3Encoding";
let DecoderMethod = "DecodeSimm18Lsl3";
+ let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def simm20 : Operand<i32> {
Modified: llvm/trunk/test/MC/Mips/mips64r6/relocations.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/relocations.s?rev=210908&r1=210907&r2=210908&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/relocations.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/relocations.s Fri Jun 13 09:26:47 2014
@@ -34,6 +34,10 @@
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar at PCREL_LO16,
# CHECK-FIXUP: kind: fixup_MIPS_PCLO16
+# CHECK-FIXUP: ldpc $2, bar # encoding: [0xec,0b010110AA,A,A]
+# CHECK-FIXUP: # fixup A - offset: 0,
+# CHECK-FIXUP: value: bar,
+# CHECK-FIXUP: kind: fixup_Mips_PC18_S3
# CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
@@ -53,8 +57,9 @@
# CHECK-ELF: 0x18 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: 0x1C R_MIPS_PCHI16 bar 0x0
# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0
-# CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0
+# CHECK-ELF: 0x24 R_MIPS_PC18_S3 bar 0x0
# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0
+# CHECK-ELF: 0x2C R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: ]
addiupc $2,bar
@@ -66,5 +71,6 @@
bc bar
aluipc $2, %pcrel_hi(bar)
addiu $2, $2, %pcrel_lo(bar)
+ ldpc $2,bar
lwpc $2,bar
lwupc $2,bar
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