RFC: add "cmpxchg weak" to LLVM IR
chandlerc at google.com
Fri Jun 13 02:47:34 PDT 2014
On Thu, Jun 12, 2014 at 5:22 PM, Tim Northover <t.p.northover at gmail.com>
> Assuming that's OK, onto the DAG level. What I'd like to do is a
> little odd, but makes sense I think:
> 1. Keep ATOMIC_CMP_SWAP with its current semantics: strong cmpxchg,
> returning just the loaded value.
> 2. Add ATOMIC_CMP_SWAP_WITH_SUCCESS (better name suggestions welcome)
> that has a second i1 value (initially) as with the IR instruction.
> It's still a strong cmpxchg.
> 3. Expanding ATOMIC_CMP_SWAP_WITH_SUCCESS will yield an
> ATOMIC_CMP_SWAP and a SETCC.
> The advantage of this scheme is that existing targets can remain
> mostly unchanged if they're not interested in the extra work required.
> LL/SC architectures will be assumed to move over to something like the
> IR level pass already used by ARM if they want weak support (or they
> can add weak DAG nodes if they're masochists). x86 can switch its
> Custom handling over to the new ATOMIC_CMP_SWAP_WITH_SUCCESS to get
> rid of the vast majority of redundant comparisons coming out of C++
> code with relative ease.
So, I see where you're going here, but I'm curious -- why not just switch
ATOMIC_CMP_SWAP to have a second i1 value, and still be strong? Is this
*just* to support expanding? I wonder if that's really useful rather than
just lowering it directly on the various targets....
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