[llvm] r210413 - start to clean up buildMI calls in mips fast-isel

[Eric Christopher]

On Thu, Jun 12, 2014 at 1:13 PM, reed kotler <rkotler at mips.com> wrote:
> On 06/12/2014 11:37 AM, Eric Christopher wrote:
>>
>> On Sat, Jun 7, 2014 at 8:04 PM, Reed Kotler <rkotler at mips.com> wrote:
>>>
>>> Author: rkotler
>>> Date: Sat Jun  7 22:04:42 2014
>>> New Revision: 210413
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=210413&view=rev
>>> Log:
>>> start to clean up buildMI calls in mips fast-isel
>>>
>>> Summary: Merge branch 'master' into 1758_6
>>>
>>> Test Plan:
>>> No functionality change. Run "make check" and run test-suite.
>>> Because our servers are not yet running again I have not yet run
>>> test-suite.
>>> I will further review myself before submission.
>>>
>> Please make actual useful commit messages. This stuff isn't useful.
>
> Sorry. This was a mistake in my use of phabricator.
> By default it copies all these local git commit messages that are not useful
> for anyone to read into the phabricator log which then gets pumped into the
> svn commit summary.
> I have to remember to delete them but I forgot to.  I'm a phabricator
> newbie.
>

Yeah, sorry, I'm a few days behind and noticed the thread after I'd sent this.

Of course, you could just put them into phab ready for commit ;)

-eric

> Reed
>
>
>> -eric
>>
>>> Reviewers: dsanders
>>>
>>> Reviewed By: dsanders
>>>
>>> Differential Revision: http://reviews.llvm.org/D3819
>>>
>>> Modified:
>>>      llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
>>> URL:
>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=210413&r1=210412&r2=210413&view=diff
>>>
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)
>>> +++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Sat Jun  7 22:04:42 2014
>>> @@ -83,7 +83,7 @@ private:
>>>     unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass
>>> *RC);
>>>
>>>     // for some reason, this default is not generated by tablegen
>>> -  // so we explicitly generate it here.
>>> +  // so we explicitly generate it here.
>>>     //
>>>     unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass
>>> *RC,
>>>                                unsigned Op0, bool Op0IsKill, uint64_t
>>> imm1,
>>> @@ -91,6 +91,20 @@ private:
>>>       return 0;
>>>     }
>>>
>>> +  MachineInstrBuilder EmitInst(unsigned Opc) {
>>> +    return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
>>> TII.get(Opc));
>>> +  }
>>> +
>>> +  MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
>>> +    return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
>>> TII.get(Opc),
>>> +                   DstReg);
>>> +  }
>>> +
>>> +  MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
>>> +                                    unsigned MemReg, int64_t MemOffset)
>>> {
>>> +    return
>>> EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
>>> +  }
>>> +
>>>   #include "MipsGenFastISel.inc"
>>>   };
>>>
>>> @@ -155,10 +169,7 @@ bool MipsFastISel::EmitStore(MVT VT, uns
>>>     //
>>>     if (VT != MVT::i32)
>>>       return false;
>>> -  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::SW))
>>> -      .addReg(SrcReg)
>>> -      .addReg(Addr.Base.Reg)
>>> -      .addImm(Addr.Offset);
>>> +  EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
>>>     return true;
>>>   }
>>>
>>> @@ -198,8 +209,7 @@ bool MipsFastISel::SelectRet(const Instr
>>>     if (Ret->getNumOperands() > 0) {
>>>       return false;
>>>     }
>>> -  unsigned RetOpc = Mips::RetRA;
>>> -  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(RetOpc));
>>> +  EmitInst(Mips::RetRA);
>>>     return true;
>>>   }
>>>
>>> @@ -233,9 +243,8 @@ unsigned MipsFastISel::MaterializeGV(con
>>>     // TLS not supported at this time.
>>>     if (IsThreadLocal)
>>>       return 0;
>>> -  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LW),
>>> DestReg)
>>> -      .addReg(MFI->getGlobalBaseReg())
>>> -      .addGlobalAddress(GV, 0, MipsII::MO_GOT);
>>> +  EmitInst(Mips::LW,
>>> DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
>>> +      GV, 0, MipsII::MO_GOT);
>>>     return DestReg;
>>>   }
>>>   unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
>>> @@ -257,15 +266,10 @@ unsigned MipsFastISel::Materialize32BitI
>>>
>>>     if (isInt<16>(Imm)) {
>>>       unsigned Opc = Mips::ADDiu;
>>> -    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
>>> ResultReg)
>>> -        .addReg(Mips::ZERO)
>>> -        .addImm(Imm);
>>> +    EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
>>>       return ResultReg;
>>>     } else if (isUInt<16>(Imm)) {
>>> -    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
>>> TII.get(Mips::ORi),
>>> -            ResultReg)
>>> -        .addReg(Mips::ZERO)
>>> -        .addImm(Imm);
>>> +    EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
>>>       return ResultReg;
>>>     }
>>>     unsigned Lo = Imm & 0xFFFF;
>>> @@ -273,16 +277,10 @@ unsigned MipsFastISel::Materialize32BitI
>>>     if (Lo) {
>>>       // Both Lo and Hi have nonzero bits.
>>>       unsigned TmpReg = createResultReg(RC);
>>> -    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
>>> TII.get(Mips::LUi),
>>> -            TmpReg).addImm(Hi);
>>> -    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
>>> TII.get(Mips::ORi),
>>> -            ResultReg)
>>> -        .addReg(TmpReg)
>>> -        .addImm(Lo);
>>> -
>>> +    EmitInst(Mips::LUi, TmpReg).addImm(Hi);
>>> +    EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
>>>     } else {
>>> -    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
>>> TII.get(Mips::LUi),
>>> -            ResultReg).addImm(Hi);
>>> +    EmitInst(Mips::LUi, ResultReg).addImm(Hi);
>>>     }
>>>     return ResultReg;
>>>   }
>>>
>>>
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>
>