[PATCH] ARMEB: Vector extend operations

James Molloy james.molloy at arm.com
Thu Jun 12 04:40:04 PDT 2014

Hi Konrad,

Thanks for the explanation. So as I understand the problem, LLVM is generating a scalar load for under-sized vectors.

I'd like to see a fuller explanation of what is going on and why in the source code and commit message. The important bits being:
  * We need to load an under-sized vector.
  * To do this we need to use a VLD1_LN to load one lane of a vector.
  * So we need to pretend that we're loading a larger vector element size than we are.
  * This means we load "as-if" VLDR, and need to perform a REV to get us back right again.

Also, the following testcase doesn't generate the best code sequence:

; CHECK-LABEL: vector_ext_2i32_to_2i64:
; CHECK:       vldr [[REG:d[0-9]+]]
; CHECK:       vrev64.32  [[REG]], [[REG]]
; CHECK:       vmovl.u32  {{q[0-9]+}}, [[REG]]

That VLDR can be a VLD1.32 dX, which means we don't need a REV. Can you please change this? I suspect this only affects extloads from 64-bit types to 128-bit types.




More information about the llvm-commits mailing list