[PATCH] ARMEB: Vector extend operations

Konrad Anheim kanheim at a-bix.com
Thu Jun 12 04:04:13 PDT 2014

Hi James,

In order to load a 2x8 vector, LLVM generates a ld1.16, to load a 2x16 
vector a ld1.32 load is utilized. Therefore VREV instructions are needed 
for a correct vector representation in registers.


Am 2014-06-12 12:01, schrieb James Molloy:
> Hi Christian,
> Could you please explain why this is necessary? I'm somewhat confused.
> We have canonicalised on using LD1 for vector loads, and our register
> content is in the form "as if" loaded by an LD1. I therefore do not
> understand why you need a VREV32 after the LD1. The lane order should
> be correct, and all you need to do is lengthen.
> In fact, we chose LD1 as our form **precisely because** we didn't want
> to change the vectorizer!
> Cheers,
> James
> http://reviews.llvm.org/D4043


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