[llvm] r210539 - SelectionDAG: Expand SELECT_CC to SELECT + SETCC

Tom Stellard tom at stellard.net
Wed Jun 11 09:33:49 PDT 2014


On Wed, Jun 11, 2014 at 08:20:05AM -0700, Arnold Schwaighofer wrote:
> Hi Tom,
> 
> SPEC2006 (FPU which contains soplex) is not available in the open source. Companies working on compilers often have licensed it.
> 
> 
> $ ls /path/to/test-suite-externals
>> speccpu2006
> 
> $ ls /path/to/test-suite-externals/speccpu2006
> Docs
> Docs.txt
> LICENSE
> LICENSE.txt
> MANIFEST
> README
> README.txt
> Revisions
> benchspec
>> 
> The llvm test suite is setup so that if you run LNT with the —test-externals it will also run SPEC if you have it placed in a directory and direct LNT to it (there is also a way to do the same thing with plain configure):
> 
> TS=/path/to/test-suite
> TSE=/path/to/test-suite-externals
> lnt runtest --submit ... nt --sandbox ... --cc $CLANGINSTALL2/bin/clang --test-suite $TS --test-externals $TSE … --only-test=External/SPEC/CFP2006/450.soplex
> 
> 
> Please let me know if you have access to spec2006.
> 
> 

I don't have access to spec2006.  What kind of failure is it, a miscompile or a crash?

-Tom

> 
> > On Jun 11, 2014, at 7:06 AM, Tom Stellard <tom at stellard.net> wrote:
> > 
> > On Tue, Jun 10, 2014 at 07:51:51PM -0700, Arnold Schwaighofer wrote:
> >> Hi Tom,
> >> 
> >> this commit seems to be breaking spec/soplex on at least mac ox x86_64 (our internal builders also seem to point to it breaking arm/aarch64).
> >> 
> >> 
> >> I can reproduce this execution failure on my machine with clang from:
> >> 
> >> 
> >> 
> >> llvm:  HEAD
> >> 
> >> 
> >> c23f0e1e446426190f563fcb89ef644927f7f438 (210540)
> >> 
> >> 
> >> clang: master
> >> 
> >> 
> >> e062e67070e0834a386cd6177aac989f91622530 (210609)
> >> 
> >> 
> >> 
> >> 
> >> 
> >> 
> >> 
> >> Do you have access to spec? Could you take a look?
> >> 
> > 
> > I'm not sure what spec is.  Where can I get it from?  If I did have spec is the
> > command below how I could reproduce the failure?  Would it be possible to send
> > me the LLVM IR from the failing test?
> > 
> > -Tom
> > 
> >> 
> >> 
> >> 
> >> Thanks,
> >> 
> >> Arnold
> >> 
> >> 
> >> 
> >> 
> >> "make" "-k" "TARGET_LLVMGCC=/Volumes/Data/backedup/dev/os/clang-trunk/release-cmake/install/bin/clang" "TARGET_CXX=None" "LLI_OPTFLAGS=-O2" "TARGET_CC=None" "TARGET_LLVMGXX=/Volumes/Data/backedup/dev/os/clang-trunk/release-cmake/install/bin/clang++" "TEST=simple" "CC_UNDER_TEST_IS_CLANG=1" "ENABLE_PARALLEL_REPORT=1" "TARGET_FLAGS=-Wno-implicit-function-declaration -Wno-incompatible-pointer-types  -isysroot ...  " "USE_REFERENCE_OUTPUT=1" "CC_UNDER_TEST_TARGET_IS_X86_64=1" "OPTFLAGS=-Os" "LLC_OPTFLAGS=-O2" "ENABLE_OPTIMIZED=1" "ARCH=x86_64" "ENABLE_HASHED_PROGRAM_OUTPUT=1" "DISABLE_JIT=1" "-C" "External/SPEC/CFP2006/450.soplex" "-j" "4" "report" "report.simple.csv"
> >> 
> >> 
> >> 
> >> 
> >> 
> >> 
> >> 
> >> 
> >> 
> >> On 06/10/14, Tom Stellard   wrote:
> >>> Author: tstellar
> >>> Date: Tue Jun 10 11:01:22 2014
> >>> New Revision: 210539
> >>> 
> >>> URL: http://llvm.org/viewvc/llvm-project?rev=210539&view=rev
> >>> Log:
> >>> SelectionDAG: Expand SELECT_CC to SELECT + SETCC
> >>> 
> >>> This consolidates code from the Hexagon, R600, and XCore targets.
> >>> 
> >>> No functionality change intended.
> >>> 
> >>> Modified:
> >>>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> >>>    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
> >>>    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
> >>>    llvm/trunk/lib/Target/R600/SIISelLowering.cpp
> >>>    llvm/trunk/lib/Target/R600/SIISelLowering.h
> >>>    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
> >>>    llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
> >>>    llvm/trunk/test/CodeGen/R600/sint_to_fp64.ll
> >>>    llvm/trunk/test/CodeGen/R600/uint_to_fp.f64.ll
> >>> 
> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=210539&r1=210538&r2=210539&view=diff
> >>> ==============================================================================
> >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jun 10 11:01:22 2014
> >>> @@ -3905,13 +3905,29 @@ void SelectionDAGLegalize::ExpandNode(SD
> >>>     Tmp2 = Node->getOperand(1);   // RHS
> >>>     Tmp3 = Node->getOperand(2);   // True
> >>>     Tmp4 = Node->getOperand(3);   // False
> >>> +    EVT VT = Node->getValueType(0);
> >>>     SDValue CC = Node->getOperand(4);
> >>> +    ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
> >>> 
> >>> +    if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
> >>> +      // If the condition code is legal, then we need to expand this
> >>> +      // node using SETCC and SELECT.
> >>> +      EVT CmpVT = Tmp1.getValueType();
> >>> +      assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
> >>> +             "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
> >>> +             "expanded.");
> >>> +      EVT CCVT = TLI.getSetCCResultType(*DAG.getContext(), CmpVT);
> >>> +      SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
> >>> +      Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
> >>> +      break;
> >>> +    }
> >>> +
> >>> +    // SELECT_CC is legal, so the condition code must not be.
> >>>     bool Legalized = false;
> >>>     // Try to legalize by inverting the condition.  This is for targets that
> >>>     // might support an ordered version of a condition, but not the unordered
> >>>     // version (or vice versa).
> >>> -    ISD::CondCode InvCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
> >>> +    ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
> >>>                                                Tmp1.getValueType().isInteger());
> >>>     if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
> >>>       // Use the new condition code and swap true and false
> >>> 
> >>> Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
> >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=210539&r1=210538&r2=210539&view=diff
> >>> ==============================================================================
> >>> --- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
> >>> +++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Tue Jun 10 11:01:22 2014
> >>> @@ -944,21 +944,6 @@ HexagonTargetLowering::LowerVASTART(SDVa
> >>> }
> >>> 
> >>> SDValue
> >>> -HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
> >>> -  SDValue LHS = Op.getOperand(0);
> >>> -  SDValue RHS = Op.getOperand(1);
> >>> -  SDValue CC = Op.getOperand(4);
> >>> -  SDValue TrueVal = Op.getOperand(2);
> >>> -  SDValue FalseVal = Op.getOperand(3);
> >>> -  SDLoc dl(Op);
> >>> -  SDNode* OpNode = Op.getNode();
> >>> -  EVT SVT = OpNode->getValueType(0);
> >>> -
> >>> -  SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i1, LHS, RHS, CC);
> >>> -  return DAG.getNode(ISD::SELECT, dl, SVT, Cond, TrueVal, FalseVal);
> >>> -}
> >>> -
> >>> -SDValue
> >>> HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
> >>>   EVT ValTy = Op.getValueType();
> >>>   SDLoc dl(Op);
> >>> @@ -1341,8 +1326,8 @@ HexagonTargetLowering::HexagonTargetLowe
> >>>     setOperationAction(ISD::BSWAP, MVT::i64, Expand);
> >>> 
> >>>     // Lower SELECT_CC to SETCC and SELECT.
> >>> -    setOperationAction(ISD::SELECT_CC, MVT::i32,   Custom);
> >>> -    setOperationAction(ISD::SELECT_CC, MVT::i64,   Custom);
> >>> +    setOperationAction(ISD::SELECT_CC, MVT::i32,   Expand);
> >>> +    setOperationAction(ISD::SELECT_CC, MVT::i64,   Expand);
> >>> 
> >>>     if (QRI->Subtarget.hasV5TOps()) {
> >>> 
> >>> @@ -1577,7 +1562,6 @@ HexagonTargetLowering::LowerOperation(SD
> >>>     case ISD::BR_JT:              return LowerBR_JT(Op, DAG);
> >>> 
> >>>     case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
> >>> -    case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
> >>>     case ISD::SELECT:             return Op;
> >>>     case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
> >>>     case ISD::INLINEASM:          return LowerINLINEASM(Op, DAG);
> >>> 
> >>> Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
> >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=210539&r1=210538&r2=210539&view=diff
> >>> ==============================================================================
> >>> --- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
> >>> +++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Tue Jun 10 11:01:22 2014
> >>> @@ -124,7 +124,6 @@ namespace llvm {
> >>>                             const SmallVectorImpl<SDValue> &OutVals,
> >>>                             SDValue Callee) const;
> >>> 
> >>> -    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
> >>>     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
> >>>     SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
> >>>     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
> >>> 
> >>> Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
> >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=210539&r1=210538&r2=210539&view=diff
> >>> ==============================================================================
> >>> --- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
> >>> +++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Tue Jun 10 11:01:22 2014
> >>> @@ -105,10 +105,10 @@ SITargetLowering::SITargetLowering(Targe
> >>>   setOperationAction(ISD::SELECT, MVT::f64, Promote);
> >>>   AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
> >>> 
> >>> -  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
> >>> -  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
> >>> -
> >>> -  setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
> >>> +  setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
> >>> +  setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
> >>> +  setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
> >>> +  setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
> >>> 
> >>>   setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
> >>>   setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
> >>> @@ -611,7 +611,6 @@ SDValue SITargetLowering::LowerOperation
> >>>   }
> >>> 
> >>>   case ISD::SELECT: return LowerSELECT(Op, DAG);
> >>> -  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
> >>>   case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
> >>>   case ISD::STORE: return LowerSTORE(Op, DAG);
> >>>   case ISD::ANY_EXTEND: // Fall-through
> >>> @@ -903,19 +902,6 @@ SDValue SITargetLowering::LowerSELECT(SD
> >>>   return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
> >>> }
> >>> 
> >>> -SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
> >>> -  SDValue LHS = Op.getOperand(0);
> >>> -  SDValue RHS = Op.getOperand(1);
> >>> -  SDValue True = Op.getOperand(2);
> >>> -  SDValue False = Op.getOperand(3);
> >>> -  SDValue CC = Op.getOperand(4);
> >>> -  EVT VT = Op.getValueType();
> >>> -  SDLoc DL(Op);
> >>> -
> >>> -  SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
> >>> -  return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
> >>> -}
> >>> -
> >>> SDValue SITargetLowering::LowerSIGN_EXTEND(SDValue Op,
> >>>                                            SelectionDAG &DAG) const {
> >>>   EVT VT = Op.getValueType();
> >>> 
> >>> Modified: llvm/trunk/lib/Target/R600/SIISelLowering.h
> >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.h?rev=210539&r1=210538&r2=210539&view=diff
> >>> ==============================================================================
> >>> --- llvm/trunk/lib/Target/R600/SIISelLowering.h (original)
> >>> +++ llvm/trunk/lib/Target/R600/SIISelLowering.h Tue Jun 10 11:01:22 2014
> >>> @@ -27,7 +27,6 @@ class SITargetLowering : public AMDGPUTa
> >>>                                SelectionDAG &DAG) const;
> >>>   SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
> >>>   SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
> >>> -  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
> >>>   SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
> >>>   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
> >>>   SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
> >>> 
> >>> Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
> >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=210539&r1=210538&r2=210539&view=diff
> >>> ==============================================================================
> >>> --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
> >>> +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Jun 10 11:01:22 2014
> >>> @@ -92,7 +92,7 @@ XCoreTargetLowering::XCoreTargetLowering
> >>> 
> >>>   // XCore does not have the NodeTypes below.
> >>>   setOperationAction(ISD::BR_CC,     MVT::i32,   Expand);
> >>> -  setOperationAction(ISD::SELECT_CC, MVT::i32,   Custom);
> >>> +  setOperationAction(ISD::SELECT_CC, MVT::i32,   Expand);
> >>>   setOperationAction(ISD::ADDC, MVT::i32, Expand);
> >>>   setOperationAction(ISD::ADDE, MVT::i32, Expand);
> >>>   setOperationAction(ISD::SUBC, MVT::i32, Expand);
> >>> @@ -217,7 +217,6 @@ LowerOperation(SDValue Op, SelectionDAG
> >>>   case ISD::BR_JT:              return LowerBR_JT(Op, DAG);
> >>>   case ISD::LOAD:               return LowerLOAD(Op, DAG);
> >>>   case ISD::STORE:              return LowerSTORE(Op, DAG);
> >>> -  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
> >>>   case ISD::VAARG:              return LowerVAARG(Op, DAG);
> >>>   case ISD::VASTART:            return LowerVASTART(Op, DAG);
> >>>   case ISD::SMUL_LOHI:          return LowerSMUL_LOHI(Op, DAG);
> >>> @@ -258,16 +257,6 @@ void XCoreTargetLowering::ReplaceNodeRes
> >>> //  Misc Lower Operation implementation
> >>> //===----------------------------------------------------------------------===//
> >>> 
> >>> -SDValue XCoreTargetLowering::
> >>> -LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
> >>> -{
> >>> -  SDLoc dl(Op);
> >>> -  SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
> >>> -                             Op.getOperand(3), Op.getOperand(4));
> >>> -  return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
> >>> -                     Op.getOperand(1));
> >>> -}
> >>> -
> >>> SDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA,
> >>>                                                      const GlobalValue *GV,
> >>>                                                      SelectionDAG &DAG) const {
> >>> 
> >>> Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
> >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.h?rev=210539&r1=210538&r2=210539&view=diff
> >>> ==============================================================================
> >>> --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.h (original)
> >>> +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Tue Jun 10 11:01:22 2014
> >>> @@ -157,7 +157,6 @@ namespace llvm {
> >>>     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
> >>>     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
> >>>     SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
> >>> -    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
> >>>     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
> >>>     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
> >>>     SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
> >>> 
> >>> Modified: llvm/trunk/test/CodeGen/R600/sint_to_fp64.ll
> >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/sint_to_fp64.ll?rev=210539&r1=210538&r2=210539&view=diff
> >>> ==============================================================================
> >>> --- llvm/trunk/test/CodeGen/R600/sint_to_fp64.ll (original)
> >>> +++ llvm/trunk/test/CodeGen/R600/sint_to_fp64.ll Tue Jun 10 11:01:22 2014
> >>> @@ -10,9 +10,11 @@ define void @sint_to_fp64(double addrspa
> >>> 
> >>> ; SI-LABEL: @sint_to_fp_i1_f64:
> >>> ; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
> >>> -; SI-NEXT: V_CNDMASK_B32_e64 [[IRESULT:v[0-9]+]], 0, -1, [[CMP]]
> >>> -; SI-NEXT: V_CVT_F64_I32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
> >>> -; SI: BUFFER_STORE_DWORDX2 [[RESULT]],
> >>> +; FIXME: We should the VGPR sources for V_CNDMASK are copied from SGPRs,
> >>> +; we should be able to fold the SGPRs into the V_CNDMASK instructions.
> >>> +; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
> >>> +; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
> >>> +; SI: BUFFER_STORE_DWORDX2
> >>> ; SI: S_ENDPGM
> >>> define void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
> >>>   %cmp = icmp eq i32 %in, 0
> >>> 
> >>> Modified: llvm/trunk/test/CodeGen/R600/uint_to_fp.f64.ll
> >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/uint_to_fp.f64.ll?rev=210539&r1=210538&r2=210539&view=diff
> >>> ==============================================================================
> >>> --- llvm/trunk/test/CodeGen/R600/uint_to_fp.f64.ll (original)
> >>> +++ llvm/trunk/test/CodeGen/R600/uint_to_fp.f64.ll Tue Jun 10 11:01:22 2014
> >>> @@ -11,9 +11,11 @@ define void @uint_to_fp_f64_i32(double a
> >>> 
> >>> ; SI-LABEL: @uint_to_fp_i1_f64:
> >>> ; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
> >>> -; SI-NEXT: V_CNDMASK_B32_e64 [[IRESULT:v[0-9]+]], 0, 1, [[CMP]]
> >>> -; SI-NEXT: V_CVT_F64_U32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
> >>> -; SI: BUFFER_STORE_DWORDX2 [[RESULT]],
> >>> +; FIXME: We should the VGPR sources for V_CNDMASK are copied from SGPRs,
> >>> +; we should be able to fold the SGPRs into the V_CNDMASK instructions.
> >>> +; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
> >>> +; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
> >>> +; SI: BUFFER_STORE_DWORDX2
> >>> ; SI: S_ENDPGM
> >>> define void @uint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
> >>>   %cmp = icmp eq i32 %in, 0
> >>> 
> >>> 
> >>> _______________________________________________
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> >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >> 
> >> 
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