[PATCH] [AArch64] Basic Sched Model for Cortex-A57

Dave Estes cestes at codeaurora.org
Fri Jun 6 08:01:08 PDT 2014


Thanks, Renato. With this patch I wanted to lay the groundwork for future refinements. Specifically, I'm speaking of the myriad SchedWrite types. These represent every combination of latency, micro-op count, and processor resource used by every instruction for the A57.  At this point, I haven't actually mapped all of these to individual instructions using SchedRWs and InstRWs; instead I've just relied mostly on the default SchedRWs. I think doing this mapping is a logical next step, but I wanted to get this basic model in the community because won't be able to work on it for another three weeks (looooooong vacation). Hopefully it's a good start and will hold folks over until I get back.

Concerning testing, I totally agree. With both the A53 and A57 sched models, I've really only provided sanity tests. This is mostly because my strategy was to write tests and evaluate the resulting schedules; and such tests are somewhat fragile. A perfect example is the change I just made in another review for the A53 (http://reviews.llvm.org/D4037). I fixed the input operand ordering in the multiply w/ accumulate family of instructions and it caused a barely related test case to fail. That test case was very fragile, as the new schedule was effectively just as good as the previous "correct" schedule. This triggered an idea, and I modified the test case to instead verify the computed latency for successor SUs. Following this approach, it will be much easier to verify the sched model changes for a subtarget without having to worry too much about unrelated patches breaking the test cases.

Anyhow, that was long winded and so the short of it is that I anticipate more test cases in the future...but not for at least three more weeks. :)

http://reviews.llvm.org/D4008






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